* [PATCH V8 1/4] arm64: dts: ti: k3-am62a: add opp frequencies
2024-10-08 13:20 [PATCH V8 0/4] arm64: dts: ti: k3-am62{a,p}x-sk: add opp frequencies Dhruva Gole
@ 2024-10-08 13:20 ` Dhruva Gole
2024-10-08 13:20 ` [PATCH V8 2/4] arm64: dts: ti: k3-am62a7-sk: add 1.4ghz opp entry Dhruva Gole
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Dhruva Gole @ 2024-10-08 13:20 UTC (permalink / raw)
To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo
Cc: linux-pm, devicetree, linux-kernel, linux-arm-kernel,
Dhruva Gole, Rob Herring, Krzysztof Kozlowski, Bryan Brattlof
From: Bryan Brattlof <bb@ti.com>
One power management technique available to the Cortex-A53s is their
ability to dynamically scale their frequency across the device's
Operating Performance Points (OPP)
The OPPs available for the Cortex-A53s on the AM62Ax can vary based on
the silicon variant used. The SoC variant is encoded into the
WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register which is used to limit
to only OPP entries the variant supports. A table of all these variants
can be found in it's data sheet[0] for the AM62Ax family.
Add the OPP table into the SoC's fdti file along with the syscon node to
describe the WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register to detect
the SoC variant.
[0] https://www.ti.com/lit/ds/symlink/am62a3.pdf
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
---
arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 5 ++
arch/arm64/boot/dts/ti/k3-am62a7.dtsi | 51 +++++++++++++++++++++
2 files changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi
index f5ac101a04df..0b1dd5390cd3 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi
@@ -17,6 +17,11 @@ chipid: chipid@14 {
reg = <0x14 0x4>;
};
+ opp_efuse_table: syscon@18 {
+ compatible = "ti,am62-opp-efuse-table", "syscon";
+ reg = <0x18 0x4>;
+ };
+
cpsw_mac_syscon: ethernet-mac-syscon@200 {
compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
reg = <0x200 0x8>;
diff --git a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi
index f86a23404e6d..6c99221beb6b 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi
@@ -48,6 +48,8 @@ cpu0: cpu@0 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
+ operating-points-v2 = <&a53_opp_table>;
+ clocks = <&k3_clks 135 0>;
};
cpu1: cpu@1 {
@@ -62,6 +64,8 @@ cpu1: cpu@1 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
+ operating-points-v2 = <&a53_opp_table>;
+ clocks = <&k3_clks 136 0>;
};
cpu2: cpu@2 {
@@ -76,6 +80,8 @@ cpu2: cpu@2 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
+ operating-points-v2 = <&a53_opp_table>;
+ clocks = <&k3_clks 137 0>;
};
cpu3: cpu@3 {
@@ -90,6 +96,51 @@ cpu3: cpu@3 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
+ operating-points-v2 = <&a53_opp_table>;
+ clocks = <&k3_clks 138 0>;
+ };
+ };
+
+ a53_opp_table: opp-table {
+ compatible = "operating-points-v2-ti-cpu";
+ opp-shared;
+ syscon = <&opp_efuse_table>;
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-supported-hw = <0x01 0x0007>;
+ clock-latency-ns = <6000000>;
+ };
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-supported-hw = <0x01 0x0007>;
+ clock-latency-ns = <6000000>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-supported-hw = <0x01 0x0007>;
+ clock-latency-ns = <6000000>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-supported-hw = <0x01 0x0007>;
+ clock-latency-ns = <6000000>;
+ };
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-supported-hw = <0x01 0x0006>;
+ clock-latency-ns = <6000000>;
+ };
+
+ opp-1250000000 {
+ opp-hz = /bits/ 64 <1250000000>;
+ opp-supported-hw = <0x01 0x0004>;
+ clock-latency-ns = <6000000>;
+ opp-suspend;
};
};
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH V8 2/4] arm64: dts: ti: k3-am62a7-sk: add 1.4ghz opp entry
2024-10-08 13:20 [PATCH V8 0/4] arm64: dts: ti: k3-am62{a,p}x-sk: add opp frequencies Dhruva Gole
2024-10-08 13:20 ` [PATCH V8 1/4] arm64: dts: ti: k3-am62a: " Dhruva Gole
@ 2024-10-08 13:20 ` Dhruva Gole
2024-10-08 13:20 ` [PATCH V8 3/4] arm64: dts: ti: k3-am62p: add opp frequencies Dhruva Gole
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Dhruva Gole @ 2024-10-08 13:20 UTC (permalink / raw)
To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo
Cc: linux-pm, devicetree, linux-kernel, linux-arm-kernel,
Dhruva Gole, Rob Herring, Krzysztof Kozlowski, Bryan Brattlof
From: Bryan Brattlof <bb@ti.com>
The AM62Ax reference board is capable of supplying 0v85 to the VDD_CORE
which allows the Cortex-A53s to operate at 1.4GHz according to chapter
7.5 of the SoC's data sheet[0]. Append the 1.4Ghz entry to the OPP table
to enable this OPP
[0] https://www.ti.com/lit/ds/symlink/am62a3.pdf
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
---
arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
index 67faf46d7a35..a6f0d87a50d8 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
@@ -68,6 +68,15 @@ wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 {
};
};
+ opp-table {
+ /* Requires VDD_CORE at 0v85 */
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-supported-hw = <0x01 0x0004>;
+ clock-latency-ns = <6000000>;
+ };
+ };
+
vmain_pd: regulator-0 {
/* TPS25750 PD CONTROLLER OUTPUT */
compatible = "regulator-fixed";
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH V8 3/4] arm64: dts: ti: k3-am62p: add opp frequencies
2024-10-08 13:20 [PATCH V8 0/4] arm64: dts: ti: k3-am62{a,p}x-sk: add opp frequencies Dhruva Gole
2024-10-08 13:20 ` [PATCH V8 1/4] arm64: dts: ti: k3-am62a: " Dhruva Gole
2024-10-08 13:20 ` [PATCH V8 2/4] arm64: dts: ti: k3-am62a7-sk: add 1.4ghz opp entry Dhruva Gole
@ 2024-10-08 13:20 ` Dhruva Gole
2024-10-08 13:20 ` [PATCH V8 4/4] arm64: dts: ti: k3-am62p5-sk: add 1.4ghz opp entry Dhruva Gole
2024-11-05 9:14 ` [PATCH V8 0/4] arm64: dts: ti: k3-am62{a,p}x-sk: add opp frequencies Vignesh Raghavendra
4 siblings, 0 replies; 6+ messages in thread
From: Dhruva Gole @ 2024-10-08 13:20 UTC (permalink / raw)
To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo
Cc: linux-pm, devicetree, linux-kernel, linux-arm-kernel,
Dhruva Gole, Rob Herring, Krzysztof Kozlowski, Bryan Brattlof
From: Bryan Brattlof <bb@ti.com>
One power management technique available to the Cortex-A53s is their
ability to dynamically scale their frequency across the device's
Operating Performance Points (OPP)
The OPPs available for the Cortex-A53s on the AM62Px can vary based on
the silicon variant used. The SoC variant is encoded into the
WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register which is used to limit
the OPP entries the SoC supports. A table of all these variants can be
found in its data sheet[0] for the AM62Px processor family.
Add the OPP table into the SoC's fdti file along with the syscon node to
describe the WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register to detect
the SoC variant.
[0] https://www.ti.com/lit/ds/symlink/am62p-q1.pdf
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
---
.../dts/ti/k3-am62p-j722s-common-wakeup.dtsi | 5 ++
arch/arm64/boot/dts/ti/k3-am62p5.dtsi | 47 +++++++++++++++++++
2 files changed, 52 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
index 315d0092e736..6f32135f00a5 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
@@ -20,6 +20,11 @@ chipid: chipid@14 {
bootph-all;
};
+ opp_efuse_table: syscon@18 {
+ compatible = "ti,am62-opp-efuse-table", "syscon";
+ reg = <0x18 0x4>;
+ };
+
cpsw_mac_syscon: ethernet-mac-syscon@200 {
compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
reg = <0x200 0x8>;
diff --git a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi
index 41f479dca455..140587d02e88 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi
@@ -47,6 +47,7 @@ cpu0: cpu@0 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
+ operating-points-v2 = <&a53_opp_table>;
clocks = <&k3_clks 135 0>;
};
@@ -62,6 +63,7 @@ cpu1: cpu@1 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
+ operating-points-v2 = <&a53_opp_table>;
clocks = <&k3_clks 136 0>;
};
@@ -77,6 +79,7 @@ cpu2: cpu@2 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
+ operating-points-v2 = <&a53_opp_table>;
clocks = <&k3_clks 137 0>;
};
@@ -92,10 +95,54 @@ cpu3: cpu@3 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
+ operating-points-v2 = <&a53_opp_table>;
clocks = <&k3_clks 138 0>;
};
};
+ a53_opp_table: opp-table {
+ compatible = "operating-points-v2-ti-cpu";
+ opp-shared;
+ syscon = <&opp_efuse_table>;
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-supported-hw = <0x01 0x0007>;
+ clock-latency-ns = <6000000>;
+ };
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-supported-hw = <0x01 0x0007>;
+ clock-latency-ns = <6000000>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-supported-hw = <0x01 0x0007>;
+ clock-latency-ns = <6000000>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-supported-hw = <0x01 0x0007>;
+ clock-latency-ns = <6000000>;
+ };
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-supported-hw = <0x01 0x0006>;
+ clock-latency-ns = <6000000>;
+ };
+
+ opp-1250000000 {
+ opp-hz = /bits/ 64 <1250000000>;
+ opp-supported-hw = <0x01 0x0004>;
+ clock-latency-ns = <6000000>;
+ opp-suspend;
+ };
+ };
+
l2_0: l2-cache0 {
compatible = "cache";
cache-unified;
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH V8 4/4] arm64: dts: ti: k3-am62p5-sk: add 1.4ghz opp entry
2024-10-08 13:20 [PATCH V8 0/4] arm64: dts: ti: k3-am62{a,p}x-sk: add opp frequencies Dhruva Gole
` (2 preceding siblings ...)
2024-10-08 13:20 ` [PATCH V8 3/4] arm64: dts: ti: k3-am62p: add opp frequencies Dhruva Gole
@ 2024-10-08 13:20 ` Dhruva Gole
2024-11-05 9:14 ` [PATCH V8 0/4] arm64: dts: ti: k3-am62{a,p}x-sk: add opp frequencies Vignesh Raghavendra
4 siblings, 0 replies; 6+ messages in thread
From: Dhruva Gole @ 2024-10-08 13:20 UTC (permalink / raw)
To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo
Cc: linux-pm, devicetree, linux-kernel, linux-arm-kernel,
Dhruva Gole, Rob Herring, Krzysztof Kozlowski, Bryan Brattlof
From: Bryan Brattlof <bb@ti.com>
The AM62Px reference board is capable of supplying 0v85 to the VDD_CORE
which allows the Cortex-A53s to operate at 1.4GHz according to chapter
6.6 of the SoC's data sheet[0] . Append the 1.4Ghz entry to the OPP
table to enable this frequency
[0] https://www.ti.com/lit/ds/symlink/am62p-q1.pdf
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
---
arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
index 3efa12bb7254..7f3dc39e12bc 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
@@ -128,6 +128,15 @@ led-0 {
};
};
+ opp-table {
+ /* Requires VDD_CORE at 0v85 */
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-supported-hw = <0x01 0x0004>;
+ clock-latency-ns = <6000000>;
+ };
+ };
+
tlv320_mclk: clk-0 {
#clock-cells = <0>;
compatible = "fixed-clock";
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH V8 0/4] arm64: dts: ti: k3-am62{a,p}x-sk: add opp frequencies
2024-10-08 13:20 [PATCH V8 0/4] arm64: dts: ti: k3-am62{a,p}x-sk: add opp frequencies Dhruva Gole
` (3 preceding siblings ...)
2024-10-08 13:20 ` [PATCH V8 4/4] arm64: dts: ti: k3-am62p5-sk: add 1.4ghz opp entry Dhruva Gole
@ 2024-11-05 9:14 ` Vignesh Raghavendra
4 siblings, 0 replies; 6+ messages in thread
From: Vignesh Raghavendra @ 2024-11-05 9:14 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Dhruva Gole
Cc: Vignesh Raghavendra, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, Rob Herring, Krzysztof Kozlowski,
Bryan Brattlof
Hi Dhruva Gole,
On Tue, 08 Oct 2024 18:50:49 +0530, Dhruva Gole wrote:
> This series adds in the OPPs for the Cortex-A53s on the AM62Ax and
> AM62Px SoC families along with the defining the
> WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID which we can use to to properly
> limit the OPPs available for that variant.
>
> Signed-off-by: Bryan Brattlof <bb@ti.com>
> Signed-off-by: Dhruva Gole <d-gole@ti.com>
>
> [...]
I have applied the following to branch ti-k3-dts-next on [1].
Thank you!
[1/4] arm64: dts: ti: k3-am62a: add opp frequencies
commit: aeedca40159c7017f3f0cfbd1ac2066e091e784c
[2/4] arm64: dts: ti: k3-am62a7-sk: add 1.4ghz opp entry
commit: 5dae00dfaf8e4a40c68c8a4d9e453cd06bc5bf19
[3/4] arm64: dts: ti: k3-am62p: add opp frequencies
commit: 76d855f0580148d8f07f1c0aa96f33cad382e6cc
[4/4] arm64: dts: ti: k3-am62p5-sk: add 1.4ghz opp entry
commit: 50f5ad2cb52f322d472dfb451881bea7d7d78d32
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh
^ permalink raw reply [flat|nested] 6+ messages in thread