From: Jessica Zhang <quic_jesszhan@quicinc.com>
To: Rob Clark <robdclark@gmail.com>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
<quic_abhinavk@quicinc.com>, Sean Paul <sean@poorly.run>,
Marijn Suijten <marijn.suijten@somainline.org>,
"David Airlie" <airlied@gmail.com>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
Simona Vetter <simona@ffwll.ch>,
Simona Vetter <simona.vetter@ffwll.ch>
Cc: quic_ebharadw@quicinc.com, linux-arm-msm@vger.kernel.org,
dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org,
linux-kernel@vger.kernel.org,
"Rob Clark" <robdclark@chromium.org>,
"Ville Syrjälä" <ville.syrjala@linux.intel.com>,
"Jessica Zhang" <quic_jesszhan@quicinc.com>
Subject: [PATCH v3 22/23] drm/msm/dpu: Reorder encoder kickoff for CWB
Date: Wed, 16 Oct 2024 18:21:28 -0700 [thread overview]
Message-ID: <20241016-concurrent-wb-v3-22-a33cf9b93835@quicinc.com> (raw)
In-Reply-To: <20241016-concurrent-wb-v3-0-a33cf9b93835@quicinc.com>
Add a helper that will handle the correct order of the encoder kickoffs
for concurrent writeback.
For concurrent writeback, the realtime encoder must always kickoff last
as it will call the trigger flush and start.
This avoids the following scenario where the writeback encoder
increments the pending kickoff count after the WB_DONE interrupt is
fired:
If the realtime encoder is kicked off first, the encoder kickoff will
flush/start the encoder and increment the pending kickoff count. The
WB_DONE interrupt then fires (before the writeback encoder is kicked
off). When the writeback encoder enters its kickoff, it will skip the
flush/start (due to CWB being enabled) and hit a frame done timeout
as the frame was kicked off (and the WB_DONE interrupt fired) without
the pending kickoff count being incremented.
In addition, the writeback timer should only start after the realtime
encoder is kicked off to ensure that we don't get timeouts when the
system has a heavy load (ex. when debug logs are enabled)
Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 74 ++++++++++++++++++++++++++------
1 file changed, 60 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 22d135c8c8be498533b6730fbd0077628b846989..c7c903b04d7f411e81d7cd1c1bf7e1f3bcec112b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -928,6 +928,45 @@ static int _dpu_crtc_wait_for_frame_done(struct drm_crtc *crtc)
return rc;
}
+static int dpu_crtc_kickoff_clone_mode(struct drm_crtc *crtc)
+{
+ struct drm_encoder *encoder;
+ struct drm_encoder *rt_encoder = NULL, *wb_encoder;
+ struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
+
+ /* Find encoder for real time display */
+ drm_for_each_encoder_mask(encoder, crtc->dev,
+ crtc->state->encoder_mask) {
+ if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
+ wb_encoder = encoder;
+ else
+ rt_encoder = encoder;
+ }
+
+ if (!rt_encoder || !wb_encoder) {
+ DRM_DEBUG_ATOMIC("real time or wb encoder not found\n");
+ return -EINVAL;
+ }
+
+ dpu_encoder_prepare_for_kickoff(wb_encoder);
+ dpu_encoder_prepare_for_kickoff(rt_encoder);
+
+ dpu_vbif_clear_errors(dpu_kms);
+
+ /*
+ * Kickoff real time encoder last as it's the encoder that
+ * will do the flush
+ */
+ dpu_encoder_kickoff(wb_encoder);
+ dpu_encoder_kickoff(rt_encoder);
+
+ /* Don't start frame done timers until the kickoffs have finished */
+ dpu_encoder_start_frame_done_timer(wb_encoder);
+ dpu_encoder_start_frame_done_timer(rt_encoder);
+
+ return 0;
+}
+
void dpu_crtc_commit_kickoff(struct drm_crtc *crtc)
{
struct drm_encoder *encoder;
@@ -952,13 +991,27 @@ void dpu_crtc_commit_kickoff(struct drm_crtc *crtc)
goto end;
}
}
- /*
- * Encoder will flush/start now, unless it has a tx pending. If so, it
- * may delay and flush at an irq event (e.g. ppdone)
- */
- drm_for_each_encoder_mask(encoder, crtc->dev,
- crtc->state->encoder_mask)
- dpu_encoder_prepare_for_kickoff(encoder);
+
+ if (drm_crtc_in_clone_mode(crtc->state)) {
+ if (dpu_crtc_kickoff_clone_mode(crtc))
+ goto end;
+ } else {
+ /*
+ * Encoder will flush/start now, unless it has a tx pending.
+ * If so, it may delay and flush at an irq event (e.g. ppdone)
+ */
+ drm_for_each_encoder_mask(encoder, crtc->dev,
+ crtc->state->encoder_mask)
+ dpu_encoder_prepare_for_kickoff(encoder);
+
+ dpu_vbif_clear_errors(dpu_kms);
+
+ drm_for_each_encoder_mask(encoder, crtc->dev,
+ crtc->state->encoder_mask) {
+ dpu_encoder_kickoff(encoder);
+ dpu_encoder_start_frame_done_timer(encoder);
+ }
+ }
if (atomic_inc_return(&dpu_crtc->frame_pending) == 1) {
/* acquire bandwidth and other resources */
@@ -968,13 +1021,6 @@ void dpu_crtc_commit_kickoff(struct drm_crtc *crtc)
dpu_crtc->play_count++;
- dpu_vbif_clear_errors(dpu_kms);
-
- drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) {
- dpu_encoder_kickoff(encoder);
- dpu_encoder_start_frame_done_timer(encoder);
- }
-
reinit_completion(&dpu_crtc->frame_done_comp);
end:
--
2.34.1
next prev parent reply other threads:[~2024-10-17 1:21 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-17 1:21 [PATCH v3 00/23] drm/msm/dpu: Add Concurrent Writeback Support for DPU 10.x+ Jessica Zhang
2024-10-17 1:21 ` [PATCH v3 01/23] drm: add clone mode check for CRTC Jessica Zhang
2024-10-17 1:21 ` [PATCH v3 02/23] drm: Add valid clones check Jessica Zhang
2024-10-17 1:21 ` [PATCH v3 03/23] drm/msm/dpu: get rid of struct dpu_rm_requirements Jessica Zhang
2024-10-31 21:29 ` Dmitry Baryshkov
2024-10-17 1:21 ` [PATCH v3 04/23] drm/msm/dpu: switch RM to use crtc_id rather than enc_id for allocation Jessica Zhang
2024-10-31 19:18 ` Abhinav Kumar
2024-10-17 1:21 ` [PATCH v3 05/23] drm/msm/dpu: move resource allocation to CRTC Jessica Zhang
2024-10-31 19:37 ` Abhinav Kumar
2024-10-31 19:53 ` Dmitry Baryshkov
2024-10-31 20:47 ` Dmitry Baryshkov
2024-10-17 1:21 ` [PATCH v3 06/23] drm/msm/dpu: fill CRTC resources in dpu_crtc.c Jessica Zhang
2024-10-31 19:46 ` Abhinav Kumar
2024-10-17 1:21 ` [PATCH v3 07/23] drm/msm/dpu: Add CWB entry to catalog for SM8650 Jessica Zhang
2024-10-17 1:21 ` [PATCH v3 08/23] drm/msm/dpu: Specify dedicated CWB pingpong blocks Jessica Zhang
2024-10-17 1:21 ` [PATCH v3 09/23] drm/msm/dpu: add devcoredumps for cwb registers Jessica Zhang
2024-10-17 1:21 ` [PATCH v3 10/23] drm/msm/dpu: Add dpu_hw_cwb abstraction for CWB block Jessica Zhang
2024-12-24 16:31 ` Dmitry Baryshkov
2024-10-17 1:21 ` [PATCH v3 11/23] drm/msm/dpu: add CWB support to dpu_hw_wb Jessica Zhang
2024-10-17 1:21 ` [PATCH v3 12/23] drm/msm/dpu: Add RM support for allocating CWB Jessica Zhang
2024-10-17 1:21 ` [PATCH v3 13/23] drm/msm/dpu: Add CWB to msm_display_topology Jessica Zhang
2024-10-17 1:21 ` [PATCH v3 14/23] drm/msm/dpu: Require modeset if clone mode status changes Jessica Zhang
2024-10-17 1:21 ` [PATCH v3 15/23] drm/msm/dpu: Fail atomic_check if CWB and CDM are enabled Jessica Zhang
2024-10-17 1:21 ` [PATCH v3 16/23] drm/msm/dpu: Reserve resources for CWB Jessica Zhang
2024-10-17 1:21 ` [PATCH v3 17/23] drm/msm/dpu: Configure CWB in writeback encoder Jessica Zhang
2024-10-17 1:21 ` [PATCH v3 18/23] drm/msm/dpu: Support CWB in dpu_hw_ctl Jessica Zhang
2024-10-17 1:21 ` [PATCH v3 19/23] drm/msm/dpu: Adjust writeback phys encoder setup for CWB Jessica Zhang
2024-10-17 1:21 ` [PATCH v3 20/23] drm/msm/dpu: Start frame done timer after encoder kickoff Jessica Zhang
2024-10-17 1:21 ` [PATCH v3 21/23] drm/msm/dpu: Skip trigger flush and start for CWB Jessica Zhang
2024-10-17 1:21 ` Jessica Zhang [this message]
2024-10-17 1:21 ` [PATCH v3 23/23] drm/msm/dpu: Set possible clones for all encoders Jessica Zhang
2024-10-17 14:31 ` [PATCH v3 00/23] drm/msm/dpu: Add Concurrent Writeback Support for DPU 10.x+ Maxime Ripard
2024-10-17 18:15 ` Abhinav Kumar
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