[PATCH v2] arm64: dts: qcom: qcs6490-rb3gen2: Add PCIe nodes

[Krishna chaitanya chundru <quic_krichai@quicinc.com>]

Enable PCIe1 controller and its corresponding PHY nodes on
qcs6490-rb3g2 platform.

SMMU v2 has limited SID's to assign dynamic SID's with the existing
logic. For now, use static iommu-map table assigning unique SID's for
each port as dynamic approach needs boarder community discussions.

PCIe switch connected to this board has 3 downstream ports and
to the one of the downstream an embedded ethernet is connected.
Assign unique SID for each downstream port and to embedded ethernet,
and also reserve a SID for the endpoints which are going to be
connected to the other two downstream ports.

As this PCIe switch is present in this platform only update iommu-map
in this platform only as other board variants might have different
PCIe topology and might need different mapping.

Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
---
Changes in v1:
- Rebased on linux-next
- Update the commit text to summerize the discussions on v1.
- Link to v1: https://lore.kernel.org/linux-arm-msm/20240207-enable_pcie-v1-1-b684afa6371c@quicinc.com/T/
---
 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 42 ++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
index 0d45662b8028..2d14bdc1ff2d 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
@@ -684,6 +684,32 @@ &mdss_edp_phy {
 	status = "okay";
 };
 
+&pcie1 {
+	perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+
+	pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>;
+	pinctrl-names = "default";
+
+	iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
+		    <0x100 &apps_smmu 0x1c81 0x1>,
+		    <0x208 &apps_smmu 0x1c84 0x1>,
+		    <0x210 &apps_smmu 0x1c85 0x1>,
+		    <0x218 &apps_smmu 0x1c86 0x1>,
+		    <0x300 &apps_smmu 0x1c87 0x1>,
+		    <0x400 &apps_smmu 0x1c88 0x1>,
+		    <0x500 &apps_smmu 0x1c89 0x1>,
+		    <0x501 &apps_smmu 0x1c90 0x1>;
+
+	status = "okay";
+};
+
+&pcie1_phy {
+	vdda-phy-supply = <&vreg_l10c_0p88>;
+	vdda-pll-supply = <&vreg_l6b_1p2>;
+
+	status = "okay";
+};
+
 &pmk8350_rtc {
 	status = "okay";
 };
@@ -819,4 +845,20 @@ lt9611_irq_pin: lt9611-irq-state {
 		drive-strength = <2>;
 		bias-disable;
 	};
+
+	pcie1_reset_n: pcie1-reset-n-state {
+		pins = "gpio2";
+		function = "gpio";
+		drive-strength = <16>;
+		output-low;
+		bias-disable;
+	};
+
+	pcie1_wake_n: pcie1-wake-n-state {
+		pins = "gpio3";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-up;
+	};
+
 };

---
base-commit: 42f7652d3eb527d03665b09edac47f85fb600924
change-id: 20241024-enable_pcie-d2ce6fead849

Best regards,
-- 
Krishna chaitanya chundru <quic_krichai@quicinc.com>