[PATCH v3 0/3] serial: 8250_dw: Introduce SG2044 uart support.

[PATCH v3 0/3] serial: 8250_dw: Introduce SG2044 uart support.

[Inochi Amaoto]

SG2044 relys on an internal divisor when calculating bitrate, which
means a wrong clock for the most common bitrates. So a quirk is needed
for this uart device to skip the set rate call and only relys on the
internal UART divisor.


Changed from v1:
1. patch 1: improve the bindings commit message.
2. patch 2: rename jh7100 quirk and rename the quirk to
            dw8250_skip_set_rate_data.

Changed from v2:
1. patch 1: add a new patch to merge the vendor specific compatibles
2. patch 2: adopt the new patch.

Inochi Amaoto (3):
  dt-bindings: serial: snps,dw-apb-uart: merge duplicate compatible
    entry.
  dt-bindings: serial: snps-dw-apb-uart: Add Sophgo SG2044 uarts
  serial: 8250_dw: Add Sophgo SG2044 quirk

 .../devicetree/bindings/serial/snps-dw-apb-uart.yaml  | 11 +++--------
 drivers/tty/serial/8250/8250_dw.c                     |  5 +++--
 2 files changed, 6 insertions(+), 10 deletions(-)

--
2.47.0

[PATCH v3 1/3] dt-bindings: serial: snps,dw-apb-uart: merge duplicate compatible entry.

[Inochi Amaoto]

Each vendor have an items entry of its own compatible, It is needless
and can be merged as it share the same base "snps,dw-apb-uart"
compatible.

Merge the duplicate compatible entry into one item entry.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Suggested-by: Conor Dooley <conor@kernel.org>
---
 .../devicetree/bindings/serial/snps-dw-apb-uart.yaml   | 10 ++--------
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
index 4cdb0dcaccf3..c104bd8446cf 100644
--- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
@@ -37,6 +37,8 @@ properties:
           - const: renesas,rzn1-uart
       - items:
           - enum:
+              - brcm,bcm11351-dw-apb-uart
+              - brcm,bcm21664-dw-apb-uart
               - rockchip,px30-uart
               - rockchip,rk1808-uart
               - rockchip,rk3036-uart
@@ -52,14 +54,6 @@ properties:
               - rockchip,rk3588-uart
               - rockchip,rv1108-uart
               - rockchip,rv1126-uart
-          - const: snps,dw-apb-uart
-      - items:
-          - enum:
-              - brcm,bcm11351-dw-apb-uart
-              - brcm,bcm21664-dw-apb-uart
-          - const: snps,dw-apb-uart
-      - items:
-          - enum:
               - starfive,jh7100-hsuart
               - starfive,jh7100-uart
               - starfive,jh7110-uart
-- 
2.47.0

Re: [PATCH v3 1/3] dt-bindings: serial: snps,dw-apb-uart: merge duplicate compatible entry.

[Krzysztof Kozlowski]

On Thu, Oct 24, 2024 at 02:21:01PM +0800, Inochi Amaoto wrote:
> Each vendor have an items entry of its own compatible, It is needless
> and can be merged as it share the same base "snps,dw-apb-uart"
> compatible.
> 
> Merge the duplicate compatible entry into one item entry.
> 
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> Suggested-by: Conor Dooley <conor@kernel.org>
> ---
>  .../devicetree/bindings/serial/snps-dw-apb-uart.yaml   | 10 ++--------
>  1 file changed, 2 insertions(+), 8 deletions(-)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH v3 2/3] dt-bindings: serial: snps-dw-apb-uart: Add Sophgo SG2044 uarts

[Inochi Amaoto]

The UART of SG2044 is modified version of the standard Synopsys
DesignWare UART. The UART on SG2044 relys on the internal divisor
and can not set right clock rate for the common bitrates.

Add compatibles string for the Sophgo SG2044 uarts.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
 Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
index c104bd8446cf..fc263e652280 100644
--- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
@@ -54,6 +54,7 @@ properties:
               - rockchip,rk3588-uart
               - rockchip,rv1108-uart
               - rockchip,rv1126-uart
+              - sophgo,sg2044-uart
               - starfive,jh7100-hsuart
               - starfive,jh7100-uart
               - starfive,jh7110-uart
-- 
2.47.0

Re: [PATCH v3 2/3] dt-bindings: serial: snps-dw-apb-uart: Add Sophgo SG2044 uarts

[Krzysztof Kozlowski]

On Thu, Oct 24, 2024 at 02:21:02PM +0800, Inochi Amaoto wrote:
> The UART of SG2044 is modified version of the standard Synopsys
> DesignWare UART. The UART on SG2044 relys on the internal divisor
> and can not set right clock rate for the common bitrates.
> 
> Add compatibles string for the Sophgo SG2044 uarts.
> 
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> ---
>  Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH v3 3/3] serial: 8250_dw: Add Sophgo SG2044 quirk

[Inochi Amaoto]

SG2044 relys on an internal divisor when calculating bitrate, which
means a wrong clock for the most common bitrates. So add a quirk for
this uart device to skip the set rate call and only relys on the
internal UART divisor.

Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
 drivers/tty/serial/8250/8250_dw.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index ab9e7f204260..51894c93c8a3 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -750,7 +750,7 @@ static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
 	.quirks = DW_UART_QUIRK_CPR_VALUE | DW_UART_QUIRK_IS_DMA_FC,
 };
 
-static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {
+static const struct dw8250_platform_data dw8250_skip_set_rate_data = {
 	.usr_reg = DW_UART_USR,
 	.quirks = DW_UART_QUIRK_SKIP_SET_RATE,
 };
@@ -760,7 +760,8 @@ static const struct of_device_id dw8250_of_match[] = {
 	{ .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
 	{ .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
 	{ .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
-	{ .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data },
+	{ .compatible = "sophgo,sg2044-uart", .data = &dw8250_skip_set_rate_data },
+	{ .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data },
 	{ /* Sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, dw8250_of_match);
-- 
2.47.0