From: Jenishkumar Maheshbhai Patel <jpatel2@marvell.com>
To: <andrew@lunn.ch>, <gregory.clement@bootlin.com>,
<sebastian.hesselbarth@gmail.com>, <robh@kernel.org>,
<krzk+dt@kernel.org>, <conor+dt@kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Cc: <salee@marvell.com>, <dingwei@marvell.com>,
Jenishkumar Maheshbhai Patel <jpatel2@marvell.com>
Subject: [PATCH 1/1] arm64: dts: marvell: use reset controller to reset mac
Date: Mon, 11 Nov 2024 23:13:50 -0800 [thread overview]
Message-ID: <20241112071350.762111-1-jpatel2@marvell.com> (raw)
change mac reset and mac reset bits to reset controller
Signed-off-by: Jenishkumar Maheshbhai Patel <jpatel2@marvell.com>
---
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
index f5aef6a23f65..f358f9809edd 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
@@ -6,7 +6,7 @@
*/
#include <dt-bindings/interrupt-controller/mvebu-icu.h>
-#define CP11X_PCIEx_MAC_RESET_BIT_MASK(n) (0x1 << 11 + ((n + 2) % 3))
+#define CP11X_PCIEx_MAC_RESET_BIT(n) (11 + ((n + 2) % 3))
#include <dt-bindings/thermal/thermal.h>
#include "armada-common.dtsi"
@@ -276,6 +276,12 @@ CP11X_LABEL(gpio2): gpio@140 {
};
};
+ CP11X_LABEL(pcie_mac_reset): pcie-mac-reset@0x440268 {
+ compatible = "snps,dw-low-reset";
+ #reset-cells = <1>;
+ reg = <0x440268 0x4>;
+ };
+
CP11X_LABEL(syscon1): system-controller@400000 {
compatible = "syscon", "simple-mfd";
reg = <0x400000 0x1000>;
@@ -548,8 +554,7 @@ CP11X_LABEL(pcie0): pcie@CP11X_PCIE0_BASE {
num-lanes = <1>;
clock-names = "core", "reg";
clocks = <&CP11X_LABEL(clk) 1 13>, <&CP11X_LABEL(clk) 1 14>;
- marvell,system-controller = <&CP11X_LABEL(syscon0)>;
- marvell,mac-reset-bit-mask = <CP11X_PCIEx_MAC_RESET_BIT_MASK(0)>;
+ resets = <&CP11X_LABEL(pcie_mac_reset) CP11X_PCIEx_MAC_RESET_BIT(0)>;
status = "disabled";
};
@@ -575,8 +580,7 @@ CP11X_LABEL(pcie1): pcie@CP11X_PCIE1_BASE {
num-lanes = <1>;
clock-names = "core", "reg";
clocks = <&CP11X_LABEL(clk) 1 11>, <&CP11X_LABEL(clk) 1 14>;
- marvell,system-controller = <&CP11X_LABEL(syscon0)>;
- marvell,mac-reset-bit-mask = <CP11X_PCIEx_MAC_RESET_BIT_MASK(1)>;
+ resets = <&CP11X_LABEL(pcie_mac_reset) CP11X_PCIEx_MAC_RESET_BIT(1)>;
status = "disabled";
};
@@ -602,8 +606,7 @@ CP11X_LABEL(pcie2): pcie@CP11X_PCIE2_BASE {
num-lanes = <1>;
clock-names = "core", "reg";
clocks = <&CP11X_LABEL(clk) 1 12>, <&CP11X_LABEL(clk) 1 14>;
- marvell,system-controller = <&CP11X_LABEL(syscon0)>;
- marvell,mac-reset-bit-mask = <CP11X_PCIEx_MAC_RESET_BIT_MASK(2)>;
+ resets = <&CP11X_LABEL(pcie_mac_reset) CP11X_PCIEx_MAC_RESET_BIT(2)>;
status = "disabled";
};
};
--
2.25.1
next reply other threads:[~2024-11-12 7:15 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-12 7:13 Jenishkumar Maheshbhai Patel [this message]
2024-11-14 14:01 ` Andrew Lunn
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