From: Lothar Rubusch <l.rubusch@gmail.com>
To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
dinguyen@kernel.org
Cc: marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v5 00/11] Add Enclustra Arria10 and Cyclone5 SoMs
Date: Sat, 16 Nov 2024 13:10:14 +0000 [thread overview]
Message-ID: <20241116131025.114542-1-l.rubusch@gmail.com> (raw)
Add device-tree support for the following SoMs:
- Mercury SA1 (cyclone5)
- Mercury+ SA2 (cyclone5)
- Mercury+ AA1 (arria10)
Further add device-tree support for the corresponding carrier boards:
- Mercury+ PE1
- Mercury+ PE3
- Mercury+ ST1
Finally, provide generic support for combinations of the above with
one of the boot-modes
- SD
- eMMC
- QSPI
All of the above can be freely combined. Combinations are covered by
the provided .dts files. This makes an already existing .dts file
obsolete. Further minor fixes of the dtbs_checks are added separtely.
The current approach is also required for corresponding bootloader
integration using dts/upstream. That's also one of the reasons for
the .dtsi split.
Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
---
v4 -> v5:
- separate generic socfpga dt fixes from this patch set. The focus of this
patch set is the dts/dtsi files and related bindings, not additional
intel/socfpga refactoring
v3 -> v4:
- add separate patch to match "snps,dwmac" compatible in corresponding
driver, required by binding check
- replace non-standard node names in .dtsi files by node names recommended
by the device tree standard v0.4
v2 -> v3:
- dropped the patch to add the socfpga clock bindings:
Documentation/devicetree/bindings/clock/altr,socfpga-a10.yaml
reason: refactoring the "altr,socfpga-" TXT files to .yaml files is a
different story involving several other files, thus can be part of a
future patch series, not related to the current upstreaming the
Enclustra DTS support, so dropped
- adjust comments on boot mode selection
- adjust titles to several bindings patches
v1 -> v2:
- split bindings and DT adjustments/additions
- add several fixes to the socfpga.dtsi and socfpga_arria10.dtsi where
bindings did not match
- extend existing bindings by properties and nods from arria10 setup
- implement the clock binding altr,socfpga-a10.yaml based on existing
text file, rudimentary datasheet study and requirements of the
particular DT setup
---
Lothar Rubusch (11):
ARM: dts: socfpga: add Enclustra boot-mode dtsi
ARM: dts: socfpga: add Enclustra base-board dtsi
ARM: dts: socfpga: add Enclustra Mercury SA1
dt-bindings: altera: add Enclustra Mercury SA1
ARM: dts: socfpga: add Enclustra Mercury+ SA2
dt-bindings: altera: add binding for Mercury+ SA2
ARM: dts: socfpga: add Mercury AA1 combinations
dt-bindings: altera: add Mercury AA1 combinations
ARM: dts: socfpga: removal of generic PE1 dts
dt-bindings: altera: removal of generic PE1 dts
ARM: dts: socfpga: add Enclustra SoM dts files
.../devicetree/bindings/arm/altera.yaml | 24 ++-
arch/arm/boot/dts/intel/socfpga/Makefile | 25 ++-
.../socfpga/socfpga_arria10_mercury_aa1.dtsi | 141 ++++++++++++++---
.../socfpga_arria10_mercury_aa1_pe1_emmc.dts | 16 ++
.../socfpga_arria10_mercury_aa1_pe1_qspi.dts | 16 ++
.../socfpga_arria10_mercury_aa1_pe1_sdmmc.dts | 16 ++
.../socfpga_arria10_mercury_aa1_pe3_emmc.dts | 16 ++
.../socfpga_arria10_mercury_aa1_pe3_qspi.dts | 16 ++
.../socfpga_arria10_mercury_aa1_pe3_sdmmc.dts | 16 ++
.../socfpga_arria10_mercury_aa1_st1_emmc.dts | 16 ++
.../socfpga_arria10_mercury_aa1_st1_qspi.dts | 16 ++
.../socfpga_arria10_mercury_aa1_st1_sdmmc.dts | 16 ++
.../socfpga/socfpga_arria10_mercury_pe1.dts | 55 -------
.../socfpga/socfpga_cyclone5_mercury_sa1.dtsi | 143 +++++++++++++++++
.../socfpga_cyclone5_mercury_sa1_pe1_emmc.dts | 16 ++
.../socfpga_cyclone5_mercury_sa1_pe1_qspi.dts | 16 ++
...socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dts | 16 ++
.../socfpga_cyclone5_mercury_sa1_pe3_emmc.dts | 16 ++
.../socfpga_cyclone5_mercury_sa1_pe3_qspi.dts | 16 ++
...socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dts | 16 ++
.../socfpga_cyclone5_mercury_sa1_st1_emmc.dts | 16 ++
.../socfpga_cyclone5_mercury_sa1_st1_qspi.dts | 16 ++
...socfpga_cyclone5_mercury_sa1_st1_sdmmc.dts | 16 ++
.../socfpga/socfpga_cyclone5_mercury_sa2.dtsi | 146 ++++++++++++++++++
.../socfpga_cyclone5_mercury_sa2_pe1_qspi.dts | 16 ++
...socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dts | 16 ++
.../socfpga_cyclone5_mercury_sa2_pe3_qspi.dts | 16 ++
...socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dts | 16 ++
.../socfpga_cyclone5_mercury_sa2_st1_qspi.dts | 16 ++
...socfpga_cyclone5_mercury_sa2_st1_sdmmc.dts | 16 ++
...cfpga_enclustra_mercury_bootmode_emmc.dtsi | 12 ++
...cfpga_enclustra_mercury_bootmode_qspi.dtsi | 8 +
...fpga_enclustra_mercury_bootmode_sdmmc.dtsi | 8 +
.../socfpga_enclustra_mercury_pe1.dtsi | 33 ++++
.../socfpga_enclustra_mercury_pe3.dtsi | 55 +++++++
.../socfpga_enclustra_mercury_st1.dtsi | 15 ++
36 files changed, 971 insertions(+), 78 deletions(-)
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_emmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_qspi.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_sdmmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_emmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_qspi.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_sdmmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_emmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_qspi.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_sdmmc.dts
delete mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_pe1.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1.dtsi
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_emmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_qspi.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_emmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_qspi.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_emmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_qspi.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_sdmmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2.dtsi
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_qspi.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_qspi.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_qspi.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_sdmmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_emmc.dtsi
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_qspi.dtsi
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_sdmmc.dtsi
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi
--
2.39.2
next reply other threads:[~2024-11-16 13:10 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-16 13:10 Lothar Rubusch [this message]
2024-11-16 13:10 ` [PATCH v5 01/11] ARM: dts: socfpga: add Enclustra boot-mode dtsi Lothar Rubusch
2024-11-16 13:10 ` [PATCH v5 02/11] ARM: dts: socfpga: add Enclustra base-board dtsi Lothar Rubusch
2024-11-16 13:10 ` [PATCH v5 03/11] ARM: dts: socfpga: add Enclustra Mercury SA1 Lothar Rubusch
2024-11-16 13:10 ` [PATCH v5 04/11] dt-bindings: altera: " Lothar Rubusch
2024-11-16 13:10 ` [PATCH v5 05/11] ARM: dts: socfpga: add Enclustra Mercury+ SA2 Lothar Rubusch
2024-11-16 13:10 ` [PATCH v5 06/11] dt-bindings: altera: add binding for " Lothar Rubusch
2024-11-16 13:10 ` [PATCH v5 07/11] ARM: dts: socfpga: add Mercury AA1 combinations Lothar Rubusch
2024-11-16 13:10 ` [PATCH v5 08/11] dt-bindings: altera: " Lothar Rubusch
2024-11-16 13:10 ` [PATCH v5 09/11] ARM: dts: socfpga: removal of generic PE1 dts Lothar Rubusch
2024-11-16 13:10 ` [PATCH v5 10/11] dt-bindings: altera: " Lothar Rubusch
2024-11-16 13:10 ` [PATCH v5 11/11] ARM: dts: socfpga: add Enclustra SoM dts files Lothar Rubusch
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