[PATCH v2 0/2] Add MediaTek SMI reset controller driver

[PATCH v2 0/2] Add MediaTek SMI reset controller driver

[Friday Yang]

Based on tag: next-20241119, linux-next/master

Refer to the discussion in the following link:
https://lore.kernel.org/all/CAFGrd9qZhObQXvm2_abqaX83xMLqxjQETB2=wXpobDWU1CnvkA@mail.gmail.com/
https://lore.kernel.org/all/CAPDyKFpokXV2gJDgowbixTvOH_5VL3B5H8eyhP+KJ5Fasm2rFg@mail.gmail.com/
SMI clamp and reset operations should be implemented in SMI driver
instead of PM driver.

When we enable/disable power domain, the SMI LARBs linked to this power
domain could be affected by the bus glitch. To avoid this issue, SMI
need to apply clamp and reset opereations.

This patch mainly add these functions:
1) Add SMI reset controller driver to implement SMI LARBs reset opereations.
2) Add bindings for describing the reset controller.

Changes v2:
- According to previous discussions in v1, divided these four
  patches into two topic separately
- Change from 'mediatek,larb-rst-syscon' to 'mediatek,larb-rst'
- Modify the description for 'mediatek,larb-rst'
- Modify the description for '#reset-cells'
- Change compatible to 'mediatek,mt8188-smi-reset'
- Add COMPILE_TEST for RESET_MTK_SMI in Kconfig
- Drop label in binding's example
- Use MMIO instead of regmap in reset controller driver

v1:
https://patchwork.kernel.org/project/linux-mediatek/patch/20240821082845.11792-2-friday.yang@mediatek.com/
https://patchwork.kernel.org/project/linux-mediatek/patch/20240821082845.11792-5-friday.yang@mediatek.com/

friday.yang (2):
  dt-bindings: reset: mediatek: Add mt8188 SMI reset control binding
  reset: mediatek: Add reset control driver for SMI

 .../bindings/reset/mediatek,smi-reset.yaml    |  53 ++++++
 drivers/reset/Kconfig                         |   9 +
 drivers/reset/Makefile                        |   1 +
 drivers/reset/reset-mediatek-smi.c            | 156 ++++++++++++++++++
 include/dt-bindings/reset/mt8188-resets.h     |  11 ++
 5 files changed, 230 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml
 create mode 100644 drivers/reset/reset-mediatek-smi.c

--
2.46.0

[PATCH v2 1/2] dt-bindings: reset: mediatek: Add mt8188 SMI reset control binding

[Friday Yang]

From: "Friday Yang" <friday.yang@mediatek.com>

To support SMI clamp and reset operation in genpd callback, add
SMI LARB reset controller in the bindings. Add index in
mt8188-resets.h to query the reset signal in the SMI reset
control driver.

Signed-off-by: Friday Yang <friday.yang@mediatek.com>
---
 .../bindings/reset/mediatek,smi-reset.yaml    | 53 +++++++++++++++++++
 include/dt-bindings/reset/mt8188-resets.h     | 11 ++++
 2 files changed, 64 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml

diff --git a/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml b/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml
new file mode 100644
index 000000000000..77a6197a9846
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2024 MediaTek Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/mediatek,smi-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek SMI Reset Controller
+
+maintainers:
+  - Friday Yang <friday.yang@mediatek.com>
+
+description: |
+  This reset controller node is used to perform reset management
+  of SMI larbs on MediaTek platform. It is used to implement various
+  reset functions required when SMI larbs apply clamp operation.
+
+  For list of all valid reset indices see
+    <dt-bindings/reset/mt8188-resets.h> for MT8188.
+
+properties:
+  compatible:
+    enum:
+      - mediatek,mt8188-smi-reset
+
+  "#reset-cells":
+    const: 1
+    description:
+      The cell should be the device ID. SMI reset controller driver could
+      query the reset signal of each SMI larb by device ID.
+
+  mediatek,larb-rst:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Phandle of each subsys clock controller. SMI larbs are located in
+      these subsys. SMI needs to parse the node of each subsys clock
+      controller to get the register address, and then apply the reset
+      operation.
+
+required:
+  - compatible
+  - "#reset-cells"
+  - mediatek,larb-rst
+
+additionalProperties: false
+
+examples:
+  - |
+    reset-controller {
+        compatible = "mediatek,mt8188-smi-reset";
+        #reset-cells = <1>;
+        mediatek,larb-rst = <&imgsys1_dip_top>;
+    };
diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h
index 5a58c54e7d20..387a4beac688 100644
--- a/include/dt-bindings/reset/mt8188-resets.h
+++ b/include/dt-bindings/reset/mt8188-resets.h
@@ -113,4 +113,15 @@
 #define MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC	52
 #define MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC	53

+#define MT8188_SMI_RST_LARB10			0
+#define MT8188_SMI_RST_LARB11A			1
+#define MT8188_SMI_RST_LARB11C			2
+#define MT8188_SMI_RST_LARB12			3
+#define MT8188_SMI_RST_LARB11B			4
+#define MT8188_SMI_RST_LARB15			5
+#define MT8188_SMI_RST_LARB16B			6
+#define MT8188_SMI_RST_LARB17B			7
+#define MT8188_SMI_RST_LARB16A			8
+#define MT8188_SMI_RST_LARB17A			9
+
 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */
--
2.46.0

Re: [PATCH v2 1/2] dt-bindings: reset: mediatek: Add mt8188 SMI reset control binding

[AngeloGioacchino Del Regno]

Il 20/11/24 07:32, Friday Yang ha scritto:
> From: "Friday Yang" <friday.yang@mediatek.com>
> 
> To support SMI clamp and reset operation in genpd callback, add
> SMI LARB reset controller in the bindings. Add index in
> mt8188-resets.h to query the reset signal in the SMI reset
> control driver.
> 
> Signed-off-by: Friday Yang <friday.yang@mediatek.com>
> ---
>   .../bindings/reset/mediatek,smi-reset.yaml    | 53 +++++++++++++++++++
>   include/dt-bindings/reset/mt8188-resets.h     | 11 ++++
>   2 files changed, 64 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml
> 
> diff --git a/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml b/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml
> new file mode 100644
> index 000000000000..77a6197a9846
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml
> @@ -0,0 +1,53 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2024 MediaTek Inc.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/reset/mediatek,smi-reset.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek SMI Reset Controller
> +
> +maintainers:
> +  - Friday Yang <friday.yang@mediatek.com>
> +
> +description: |
> +  This reset controller node is used to perform reset management
> +  of SMI larbs on MediaTek platform. It is used to implement various
> +  reset functions required when SMI larbs apply clamp operation.
> +
> +  For list of all valid reset indices see
> +    <dt-bindings/reset/mt8188-resets.h> for MT8188.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - mediatek,mt8188-smi-reset
> +
> +  "#reset-cells":
> +    const: 1
> +    description:
> +      The cell should be the device ID. SMI reset controller driver could
> +      query the reset signal of each SMI larb by device ID.
> +
> +  mediatek,larb-rst:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description:
> +      Phandle of each subsys clock controller. SMI larbs are located in
> +      these subsys. SMI needs to parse the node of each subsys clock
> +      controller to get the register address, and then apply the reset
> +      operation.
> +
> +required:
> +  - compatible
> +  - "#reset-cells"
> +  - mediatek,larb-rst
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    reset-controller {
> +        compatible = "mediatek,mt8188-smi-reset";
> +        #reset-cells = <1>;
> +        mediatek,larb-rst = <&imgsys1_dip_top>;

I don't understand why would you be unable to add the SMI resets to the already
currently supported reset code in the clock-controller driver itself, like done
with literally all of the other clock controllers.

Please clarify.

Regards,
Angelo

Re: [PATCH v2 1/2] dt-bindings: reset: mediatek: Add mt8188 SMI reset control binding

[CK Hu (胡俊光)]

Hi, Friday:

On Wed, 2024-11-20 at 14:32 +0800, Friday Yang wrote:
> From: "Friday Yang" <friday.yang@mediatek.com>
> 
> To support SMI clamp and reset operation in genpd callback, add
> SMI LARB reset controller in the bindings. Add index in
> mt8188-resets.h to query the reset signal in the SMI reset
> control driver.
> 
> Signed-off-by: Friday Yang <friday.yang@mediatek.com>
> ---
>  .../bindings/reset/mediatek,smi-reset.yaml    | 53 +++++++++++++++++++
>  include/dt-bindings/reset/mt8188-resets.h     | 11 ++++
>  2 files changed, 64 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml
> 
> diff --git a/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml b/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml
> new file mode 100644
> index 000000000000..77a6197a9846
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml
> @@ -0,0 +1,53 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2024 MediaTek Inc.
> +%YAML 1.2
> +---
> +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/reset/mediatek,smi-reset.yaml*__;Iw!!CTRNKA9wMg0ARbw!gdXglQJh0-FDFibSUah2aNWBcdxp70BO2OQgeO0iq660S3-nixB7L2xJnKDsMlilUnctbSbP9KNv_Ot8e2aDow$ 
> +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!gdXglQJh0-FDFibSUah2aNWBcdxp70BO2OQgeO0iq660S3-nixB7L2xJnKDsMlilUnctbSbP9KNv_OvQ-6vNSA$ 
> +
> +title: MediaTek SMI Reset Controller
> +
> +maintainers:
> +  - Friday Yang <friday.yang@mediatek.com>
> +
> +description: |
> +  This reset controller node is used to perform reset management
> +  of SMI larbs on MediaTek platform. It is used to implement various
> +  reset functions required when SMI larbs apply clamp operation.
> +
> +  For list of all valid reset indices see
> +    <dt-bindings/reset/mt8188-resets.h> for MT8188.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - mediatek,mt8188-smi-reset
> +
> +  "#reset-cells":
> +    const: 1
> +    description:
> +      The cell should be the device ID. SMI reset controller driver could
> +      query the reset signal of each SMI larb by device ID.
> +
> +  mediatek,larb-rst:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description:
> +      Phandle of each subsys clock controller. SMI larbs are located in
> +      these subsys. SMI needs to parse the node of each subsys clock
> +      controller to get the register address, and then apply the reset
> +      operation.
> +
> +required:
> +  - compatible
> +  - "#reset-cells"
> +  - mediatek,larb-rst
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    reset-controller {
> +        compatible = "mediatek,mt8188-smi-reset";
> +        #reset-cells = <1>;
> +        mediatek,larb-rst = <&imgsys1_dip_top>;

It seems that imgsys1-dip-top device [1] is a syscon (system controller) device not a pure clock controller.
It is similar to mmsys device [2].
mmsys driver is in [3].
Because clock maintainer insist on placing clock control part in clock driver folder,
so the clock control sub driver is in [4].
The reset control is in mmsys main driver, and main driver would probe the clock sub driver.
Refer to mmsys device to refine imgsys1-dip-top device.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml?h=v6.12#n37
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml?h=v6.12
[3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/soc/mediatek/mtk-mmsys.c?h=v6.12
[4] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/mediatek/clk-mt8188-vdo0.c?h=v6.12

Regards,
CK

> +    };
> diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h
> index 5a58c54e7d20..387a4beac688 100644
> --- a/include/dt-bindings/reset/mt8188-resets.h
> +++ b/include/dt-bindings/reset/mt8188-resets.h
> @@ -113,4 +113,15 @@
>  #define MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC	52
>  #define MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC	53
> 
> +#define MT8188_SMI_RST_LARB10			0
> +#define MT8188_SMI_RST_LARB11A			1
> +#define MT8188_SMI_RST_LARB11C			2
> +#define MT8188_SMI_RST_LARB12			3
> +#define MT8188_SMI_RST_LARB11B			4
> +#define MT8188_SMI_RST_LARB15			5
> +#define MT8188_SMI_RST_LARB16B			6
> +#define MT8188_SMI_RST_LARB17B			7
> +#define MT8188_SMI_RST_LARB16A			8
> +#define MT8188_SMI_RST_LARB17A			9
> +
>  #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */
> --
> 2.46.0
> 
> 

Re: [PATCH v2 1/2] dt-bindings: reset: mediatek: Add mt8188 SMI reset control binding

[Krzysztof Kozlowski]

On Wed, Nov 20, 2024 at 02:32:55PM +0800, Friday Yang wrote:
> From: "Friday Yang" <friday.yang@mediatek.com>
> 
> To support SMI clamp and reset operation in genpd callback, add
> SMI LARB reset controller in the bindings. Add index in
> mt8188-resets.h to query the reset signal in the SMI reset
> control driver.
> 
> Signed-off-by: Friday Yang <friday.yang@mediatek.com>
> ---
>  .../bindings/reset/mediatek,smi-reset.yaml    | 53 +++++++++++++++++++
>  include/dt-bindings/reset/mt8188-resets.h     | 11 ++++
>  2 files changed, 64 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml
> 
> diff --git a/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml b/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml
> new file mode 100644
> index 000000000000..77a6197a9846
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml
> @@ -0,0 +1,53 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2024 MediaTek Inc.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/reset/mediatek,smi-reset.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek SMI Reset Controller
> +
> +maintainers:
> +  - Friday Yang <friday.yang@mediatek.com>
> +
> +description: |
> +  This reset controller node is used to perform reset management
> +  of SMI larbs on MediaTek platform. It is used to implement various
> +  reset functions required when SMI larbs apply clamp operation.
> +
> +  For list of all valid reset indices see
> +    <dt-bindings/reset/mt8188-resets.h> for MT8188.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - mediatek,mt8188-smi-reset
> +

Where is MMIO space?

> +  "#reset-cells":
> +    const: 1
> +    description:
> +      The cell should be the device ID. SMI reset controller driver could
> +      query the reset signal of each SMI larb by device ID.
> +
> +  mediatek,larb-rst:
> +    $ref: /schemas/types.yaml#/definitions/phandle

Ah, here it is? No, that is not how you access device MMIO. Use reg
property for this. That's a gross misrepresentation of hardware.

Best regards,
Krzysztof

[PATCH v2 2/2] reset: mediatek: Add reset controller driver for SMI

[Friday Yang]

From: "Friday Yang" <friday.yang@mediatek.com>

In order to avoid the bus glitch issue, add a reset-controller
driver for performing reset management of SMI LARBs on MediaTek
platform.

Signed-off-by: Friday Yang <friday.yang@mediatek.com>
---
 drivers/reset/Kconfig              |   9 ++
 drivers/reset/Makefile             |   1 +
 drivers/reset/reset-mediatek-smi.c | 156 +++++++++++++++++++++++++++++
 3 files changed, 166 insertions(+)
 create mode 100644 drivers/reset/reset-mediatek-smi.c

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 5b3abb6db248..07e606e530fc 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -153,6 +153,15 @@ config RESET_MCHP_SPARX5
 	help
 	  This driver supports switch core reset for the Microchip Sparx5 SoC.

+config RESET_MTK_SMI
+	bool "MediaTek SMI Reset Driver"
+	depends on MTK_SMI || COMPILE_TEST
+	help
+	  This option enables the reset controller driver for MediaTek SMI.
+	  This reset driver is responsible for managing the reset signals
+	  for SMI larbs. Say Y if you want to control reset signals for
+	  MediaTek SMI larbs. Otherwise, say N.
+
 config RESET_NPCM
 	bool "NPCM BMC Reset Driver" if COMPILE_TEST
 	default ARCH_NPCM
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 677c4d1e2632..1f5ba5696872 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_RESET_K210) += reset-k210.o
 obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
 obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
 obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o
+obj-$(CONFIG_RESET_MTK_SMI) += reset-mediatek-smi.o
 obj-$(CONFIG_RESET_NPCM) += reset-npcm.o
 obj-$(CONFIG_RESET_NUVOTON_MA35D1) += reset-ma35d1.o
 obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
diff --git a/drivers/reset/reset-mediatek-smi.c b/drivers/reset/reset-mediatek-smi.c
new file mode 100644
index 000000000000..0a2ffd9db670
--- /dev/null
+++ b/drivers/reset/reset-mediatek-smi.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Reset driver for MediaTek SMI module
+ *
+ * Copyright (C) 2024 MediaTek Inc.
+ */
+
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+
+#include <dt-bindings/reset/mt8188-resets.h>
+
+#define to_mtk_smi_reset_data(_rcdev)	\
+	container_of(_rcdev, struct mtk_smi_reset_data, rcdev)
+
+struct mtk_smi_larb_reset {
+	unsigned int	offset;
+	unsigned int	value;
+};
+
+static const struct mtk_smi_larb_reset rst_signal_mt8188[] = {
+	[MT8188_SMI_RST_LARB10]		= { 0xC, BIT(0) },
+	[MT8188_SMI_RST_LARB11A]	= { 0xC, BIT(0) },
+	[MT8188_SMI_RST_LARB11C]	= { 0xC, BIT(0) },
+	[MT8188_SMI_RST_LARB12]		= { 0xC, BIT(8) },
+	[MT8188_SMI_RST_LARB11B]	= { 0xC, BIT(0) },
+	[MT8188_SMI_RST_LARB15]		= { 0xC, BIT(0) },
+	[MT8188_SMI_RST_LARB16B]	= { 0xA0, BIT(4) },
+	[MT8188_SMI_RST_LARB17B]	= { 0xA0, BIT(4) },
+	[MT8188_SMI_RST_LARB16A]	= { 0xA0, BIT(4) },
+	[MT8188_SMI_RST_LARB17A]	= { 0xA0, BIT(4) },
+};
+
+struct mtk_smi_larb_plat {
+	const struct mtk_smi_larb_reset	*reset_signal;
+	const unsigned int		larb_reset_nr;
+};
+
+struct mtk_smi_reset_data {
+	const struct mtk_smi_larb_plat	*larb_plat;
+	struct reset_controller_dev	rcdev;
+	void __iomem			*base;
+};
+
+static const struct mtk_smi_larb_plat mtk_smi_larb_mt8188 = {
+	.reset_signal = rst_signal_mt8188,
+	.larb_reset_nr = ARRAY_SIZE(rst_signal_mt8188),
+};
+
+static int mtk_smi_larb_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+	struct mtk_smi_reset_data *data = to_mtk_smi_reset_data(rcdev);
+	const struct mtk_smi_larb_plat *larb_plat = data->larb_plat;
+	const struct mtk_smi_larb_reset *larb_rst = larb_plat->reset_signal + id;
+	unsigned int val, offset = larb_rst->offset;
+	void __iomem *base = data->base;
+
+	val = readl(base + offset);
+	val |= larb_rst->value;
+	writel(val, base + offset);
+
+	return 0;
+}
+
+static int mtk_smi_larb_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+	struct mtk_smi_reset_data *data = to_mtk_smi_reset_data(rcdev);
+	const struct mtk_smi_larb_plat *larb_plat = data->larb_plat;
+	const struct mtk_smi_larb_reset *larb_rst = larb_plat->reset_signal + id;
+	unsigned int val, offset = larb_rst->offset;
+	void __iomem *base = data->base;
+
+	val = readl(base + offset);
+	val &= ~larb_rst->value;
+	writel(val, base + offset);
+
+	return 0;
+}
+
+static int mtk_smi_larb_reset(struct reset_controller_dev *rcdev, unsigned long id)
+{
+	mtk_smi_larb_reset_assert(rcdev, id);
+
+	return mtk_smi_larb_reset_deassert(rcdev, id);
+}
+
+static const struct reset_control_ops mtk_smi_reset_ops = {
+	.reset		= mtk_smi_larb_reset,
+	.assert		= mtk_smi_larb_reset_assert,
+	.deassert	= mtk_smi_larb_reset_deassert,
+};
+
+static int mtk_smi_reset_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	const struct mtk_smi_larb_plat *larb_plat = of_device_get_match_data(dev);
+	struct device_node *np = dev->of_node, *reset_node;
+	struct mtk_smi_reset_data *data;
+	struct resource res;
+	void __iomem *base;
+
+	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	reset_node = of_parse_phandle(np, "mediatek,larb-rst", 0);
+	if (!reset_node)
+		return -EINVAL;
+
+	if (of_address_to_resource(reset_node, 0, &res)) {
+		of_node_put(reset_node);
+		return -EINVAL;
+	}
+
+	base = devm_ioremap_resource(dev, &res);
+	if (IS_ERR(base)) {
+		of_node_put(reset_node);
+		return PTR_ERR(base);
+	}
+
+	of_node_put(reset_node);
+	data->larb_plat = larb_plat;
+	data->base = base;
+	data->rcdev.owner = THIS_MODULE;
+	data->rcdev.ops = &mtk_smi_reset_ops;
+	data->rcdev.of_node = np;
+	data->rcdev.nr_resets = larb_plat->larb_reset_nr;
+	data->rcdev.dev = dev;
+	platform_set_drvdata(pdev, data);
+
+	return devm_reset_controller_register(dev, &data->rcdev);
+}
+
+static const struct of_device_id mtk_smi_larb_reset_of_match[] = {
+	{ .compatible = "mediatek,mt8188-smi-reset", .data = &mtk_smi_larb_mt8188 },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, mtk_smi_larb_reset_of_match);
+
+static struct platform_driver mtk_smi_reset_driver = {
+	.probe = mtk_smi_reset_probe,
+	.driver = {
+		.name = "mediatek-smi-reset",
+		.of_match_table = mtk_smi_larb_reset_of_match,
+	},
+};
+module_platform_driver(mtk_smi_reset_driver);
+
+MODULE_AUTHOR("Friday.Yang@mediatek.com");
+MODULE_DESCRIPTION("MediaTek SMI Reset Driver");
+MODULE_LICENSE("GPL");
--
2.46.0