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From: Linu Cherian <lcherian@marvell.com>
To: <suzuki.poulose@arm.com>, <mike.leach@linaro.org>, <james.clark@arm.com>
Cc: <linux-arm-kernel@lists.infradead.org>,
	<coresight@lists.linaro.org>, <linux-kernel@vger.kernel.org>,
	<linux-doc@vger.kernel.org>, <robh@kernel.org>,
	<krzk+dt@kernel.org>, <conor+dt@kernel.org>, <corbet@lwn.net>,
	<devicetree@vger.kernel.org>, <sgoutham@marvell.com>,
	<gcherian@marvell.com>, Linu Cherian <lcherian@marvell.com>
Subject: [PATCH v13 3/8] coresight: core: Add provision for panic callbacks
Date: Mon, 16 Dec 2024 11:00:09 +0530	[thread overview]
Message-ID: <20241216053014.3427909-4-lcherian@marvell.com> (raw)
In-Reply-To: <20241216053014.3427909-1-lcherian@marvell.com>

Panic callback handlers allows coresight device drivers to sync
relevant trace data and trace metadata to reserved memory
regions so that they can be retrieved later in the subsequent
boot or in the crashdump kernel.

Signed-off-by: Linu Cherian <lcherian@marvell.com>
Reviewed-by: James Clark <james.clark@arm.com>
---
Changelog from v12:
No changes.

 drivers/hwtracing/coresight/coresight-core.c | 42 ++++++++++++++++++++
 include/linux/coresight.h                    | 12 ++++++
 2 files changed, 54 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
index ea38ecf26fcb..8c5fb66911a5 100644
--- a/drivers/hwtracing/coresight/coresight-core.c
+++ b/drivers/hwtracing/coresight/coresight-core.c
@@ -19,6 +19,7 @@
 #include <linux/property.h>
 #include <linux/delay.h>
 #include <linux/pm_runtime.h>
+#include <linux/panic_notifier.h>
 
 #include "coresight-etm-perf.h"
 #include "coresight-priv.h"
@@ -1378,6 +1379,36 @@ const struct bus_type coresight_bustype = {
 	.name	= "coresight",
 };
 
+static int coresight_panic_sync(struct device *dev, void *data)
+{
+	int mode;
+	struct coresight_device *csdev;
+
+	/* Run through panic sync handlers for all enabled devices */
+	csdev = container_of(dev, struct coresight_device, dev);
+	mode = coresight_get_mode(csdev);
+
+	if ((mode == CS_MODE_SYSFS) || (mode == CS_MODE_PERF)) {
+		if (panic_ops(csdev))
+			panic_ops(csdev)->sync(csdev);
+	}
+
+	return 0;
+}
+
+static int coresight_panic_cb(struct notifier_block *self,
+			       unsigned long v, void *p)
+{
+	bus_for_each_dev(&coresight_bustype, NULL, NULL,
+				 coresight_panic_sync);
+
+	return 0;
+}
+
+static struct notifier_block coresight_notifier = {
+	.notifier_call = coresight_panic_cb,
+};
+
 static int __init coresight_init(void)
 {
 	int ret;
@@ -1390,11 +1421,20 @@ static int __init coresight_init(void)
 	if (ret)
 		goto exit_bus_unregister;
 
+	/* Register function to be called for panic */
+	ret = atomic_notifier_chain_register(&panic_notifier_list,
+					     &coresight_notifier);
+	if (ret)
+		goto exit_perf;
+
 	/* initialise the coresight syscfg API */
 	ret = cscfg_init();
 	if (!ret)
 		return 0;
 
+	atomic_notifier_chain_unregister(&panic_notifier_list,
+					     &coresight_notifier);
+exit_perf:
 	etm_perf_exit();
 exit_bus_unregister:
 	bus_unregister(&coresight_bustype);
@@ -1404,6 +1444,8 @@ static int __init coresight_init(void)
 static void __exit coresight_exit(void)
 {
 	cscfg_exit();
+	atomic_notifier_chain_unregister(&panic_notifier_list,
+					     &coresight_notifier);
 	etm_perf_exit();
 	bus_unregister(&coresight_bustype);
 }
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index c13342594278..2e63f7614551 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -335,6 +335,7 @@ enum cs_mode {
 #define link_ops(csdev)		csdev->ops->link_ops
 #define helper_ops(csdev)	csdev->ops->helper_ops
 #define ect_ops(csdev)		csdev->ops->ect_ops
+#define panic_ops(csdev)	csdev->ops->panic_ops
 
 /**
  * struct coresight_ops_sink - basic operations for a sink
@@ -404,11 +405,22 @@ struct coresight_ops_helper {
 	int (*disable)(struct coresight_device *csdev, void *data);
 };
 
+
+/**
+ * struct coresight_ops_panic - Generic device ops for panic handing
+ *
+ * @sync	: Sync the device register state/trace data
+ */
+struct coresight_ops_panic {
+	int (*sync)(struct coresight_device *csdev);
+};
+
 struct coresight_ops {
 	const struct coresight_ops_sink *sink_ops;
 	const struct coresight_ops_link *link_ops;
 	const struct coresight_ops_source *source_ops;
 	const struct coresight_ops_helper *helper_ops;
+	const struct coresight_ops_panic *panic_ops;
 };
 
 static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa,
-- 
2.34.1


  parent reply	other threads:[~2024-12-16  5:30 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-12-16  5:30 [PATCH v13 0/8] Coresight for Kernel panic and watchdog reset Linu Cherian
2024-12-16  5:30 ` [PATCH v13 1/8] dt-bindings: arm: coresight-tmc: Add "memory-region" property Linu Cherian
2024-12-16  5:30 ` [PATCH v13 2/8] coresight: tmc-etr: Add support to use reserved trace memory Linu Cherian
2024-12-16  5:30 ` Linu Cherian [this message]
2024-12-16  5:30 ` [PATCH v13 4/8] coresight: tmc: Enable panic sync handling Linu Cherian
2024-12-16  5:30 ` [PATCH v13 5/8] coresight: tmc: Add support for reading crash data Linu Cherian
2025-01-21 14:56   ` Suzuki K Poulose
2025-02-04 11:57     ` Linu Cherian
2024-12-16  5:30 ` [PATCH v13 6/8] coresight: tmc: Stop trace capture on FlIn Linu Cherian
2024-12-16  5:30 ` [PATCH v13 7/8] coresight: config: Add preloaded configuration Linu Cherian
2024-12-16  5:30 ` [PATCH v13 8/8] Documentation: coresight: Panic support Linu Cherian
2025-01-15 10:20 ` [PATCH v13 0/8] Coresight for Kernel panic and watchdog reset Linu Cherian
2025-01-24 12:08 ` James Clark
2025-02-04 12:02   ` Linu Cherian
2025-02-11 10:41     ` James Clark

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