[PATCH v2 0/6] mips: dts: ralink: update system controller nodes and its consumers

[PATCH v2 0/6] mips: dts: ralink: update system controller nodes and its consumers

[Sergio Paracuellos]

Hi all!

Ralinks SoCs have a system controller node which serves as clock and reset
providers for the rest of the world. This patch series introduces clock and reset
definitions for these SoCs. The clocks are registered in the driver using
a bunch of arrays in specific order so these definitions represent the assigned
identifier that is used when this happens so client nodes can easily use it
to specify the clock which they consume without the need of checking driver code.
For the resets the definitions are the reset related bits in reset register of the
system controller node.

DTS files which are currently on tree are not matching system controller bindings. So
all of them are updated to properly match them.

I'd like this series to go through kernel mips git tree if possible.

Thanks in advance for your time.

Changes in v2:
- Redo commit messages in all the patches in the series to clarify why the changes
  are needed asked by Krzysztof in v1.
  
v1 of this series:
- https://lore.kernel.org/linux-clk/20250115153019.407646-1-sergio.paracuellos@gmail.com/T/#t

Best regards,
    Sergio Paracuellos

Sergio Paracuellos (6):
  dt-bindings: clock: add clock and reset definitions for Ralink SoCs
  mips: dts: ralink: rt2880: update system controller node and its
    consumers
  mips: dts: ralink: rt3050: update system controller node and its
    consumers
  mips: dts: ralink: rt3883: update system controller node and its
    consumers
  mips: dts: ralink: mt7620a: update system controller node and its
    consumers
  mips: dts: ralink: mt7628a: update system controller node and its
    consumers

 .../bindings/clock/mediatek,mtmips-sysc.yaml  |  18 ++-
 arch/mips/boot/dts/ralink/mt7620a.dtsi        |  10 +-
 arch/mips/boot/dts/ralink/mt7628a.dtsi        |  43 +++--
 arch/mips/boot/dts/ralink/rt2880.dtsi         |  10 +-
 arch/mips/boot/dts/ralink/rt3050.dtsi         |  10 +-
 arch/mips/boot/dts/ralink/rt3883.dtsi         |  10 +-
 .../dt-bindings/clock/mediatek,mtmips-sysc.h  | 130 +++++++++++++++
 .../dt-bindings/reset/mediatek,mtmips-sysc.h  | 152 ++++++++++++++++++
 8 files changed, 357 insertions(+), 26 deletions(-)
 create mode 100644 include/dt-bindings/clock/mediatek,mtmips-sysc.h
 create mode 100644 include/dt-bindings/reset/mediatek,mtmips-sysc.h

-- 
2.25.1

[PATCH v2 1/6] dt-bindings: clock: add clock and reset definitions for Ralink SoCs

[Sergio Paracuellos]

Add clock and reset missing definitions for RT2880, RT305X, RT3352, RT3383,
RT5350, MT7620 and MT76X8 Ralink SoCs. Update bindings to clarify clock and
reset cells depending on these new introduced constants so consumer nodes
can easily use the correct one in DTS files matching properly what is
being used in driver code (clock IDs and reset bits are implicitly used
there).

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 .../bindings/clock/mediatek,mtmips-sysc.yaml  |  18 ++-
 .../dt-bindings/clock/mediatek,mtmips-sysc.h  | 130 +++++++++++++++
 .../dt-bindings/reset/mediatek,mtmips-sysc.h  | 152 ++++++++++++++++++
 3 files changed, 298 insertions(+), 2 deletions(-)
 create mode 100644 include/dt-bindings/clock/mediatek,mtmips-sysc.h
 create mode 100644 include/dt-bindings/reset/mediatek,mtmips-sysc.h

diff --git a/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml b/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
index ba7ffc5b16a0..3d60e65836ed 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
@@ -18,6 +18,15 @@ description: |
   These SoCs have an XTAL from where the cpu clock is
   provided as well as derived clocks for the bus and the peripherals.
 
+  Each clock is assigned an identifier and client nodes use this identifier
+  to specify the clock which they consume.
+
+  All these identifiers could be found in:
+  [1]: <include/dt-bindings/clock/mediatek,mtmips-sysc.h>.
+
+  Reset related bits are defined in:
+  [2]: <include/dt-bindings/reset/mediatek,mtmips-sysc.h>.
+
 properties:
   compatible:
     items:
@@ -38,12 +47,14 @@ properties:
 
   '#clock-cells':
     description:
-      The first cell indicates the clock number.
+      The first cell indicates the clock number, see [1] for available
+      clocks.
     const: 1
 
   '#reset-cells':
     description:
-      The first cell indicates the reset bit within the register.
+      The first cell indicates the reset bit within the register, see
+      [2] for available resets.
     const: 1
 
 required:
@@ -56,6 +67,9 @@ additionalProperties: false
 
 examples:
   - |
+    #include <dt-bindings/clock/mediatek,mtmips-sysc.h>
+    #include <dt-bindings/reset/mediatek,mtmips-sysc.h>
+
     syscon@0 {
       compatible = "ralink,rt5350-sysc", "syscon";
       reg = <0x0 0x100>;
diff --git a/include/dt-bindings/clock/mediatek,mtmips-sysc.h b/include/dt-bindings/clock/mediatek,mtmips-sysc.h
new file mode 100644
index 000000000000..a03335b0e077
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mtmips-sysc.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MTMIPS_H
+#define _DT_BINDINGS_CLK_MTMIPS_H
+
+/* Ralink RT-2880 clocks */
+
+#define RT2880_CLK_XTAL		0
+#define RT2880_CLK_CPU		1
+#define RT2880_CLK_BUS		2
+#define RT2880_CLK_TIMER	3
+#define RT2880_CLK_WATCHDOG	4
+#define RT2880_CLK_UART		5
+#define RT2880_CLK_I2C		6
+#define RT2880_CLK_UARTLITE	7
+#define RT2880_CLK_ETHERNET	8
+#define RT2880_CLK_WMAC		9
+
+/* Ralink RT-305X clocks */
+
+#define RT305X_CLK_XTAL		0
+#define RT305X_CLK_CPU		1
+#define RT305X_CLK_BUS		2
+#define RT305X_CLK_TIMER	3
+#define RT305X_CLK_WATCHDOG	4
+#define RT305X_CLK_UART		5
+#define RT305X_CLK_I2C		6
+#define RT305X_CLK_I2S		7
+#define RT305X_CLK_SPI1		8
+#define RT305X_CLK_SPI2		9
+#define RT305X_CLK_UARTLITE	10
+#define RT305X_CLK_ETHERNET	11
+#define RT305X_CLK_WMAC		12
+
+/* Ralink RT-3352 clocks */
+
+#define RT3352_CLK_XTAL		0
+#define RT3352_CLK_CPU		1
+#define RT3352_CLK_PERIPH	2
+#define RT3352_CLK_BUS		3
+#define RT3352_CLK_TIMER	4
+#define RT3352_CLK_WATCHDOG	5
+#define RT3352_CLK_UART		6
+#define RT3352_CLK_I2C		7
+#define RT3352_CLK_I2S		8
+#define RT3352_CLK_SPI1		9
+#define RT3352_CLK_SPI2		10
+#define RT3352_CLK_UARTLITE	11
+#define RT3352_CLK_ETHERNET	12
+#define RT3352_CLK_WMAC		13
+
+/* Ralink RT-3883 clocks */
+
+#define RT3883_CLK_XTAL		0
+#define RT3883_CLK_CPU		1
+#define RT3883_CLK_BUS		2
+#define RT3883_CLK_PERIPH	3
+#define RT3883_CLK_TIMER	4
+#define RT3883_CLK_WATCHDOG	5
+#define RT3883_CLK_UART		6
+#define RT3883_CLK_I2C		7
+#define RT3883_CLK_I2S		8
+#define RT3883_CLK_SPI1		9
+#define RT3883_CLK_SPI2		10
+#define RT3883_CLK_UARTLITE	11
+#define RT3883_CLK_ETHERNET	12
+#define RT3883_CLK_WMAC		13
+
+/* Ralink RT-5350 clocks */
+
+#define RT5350_CLK_XTAL		0
+#define RT5350_CLK_CPU		1
+#define RT5350_CLK_BUS		2
+#define RT5350_CLK_PERIPH	3
+#define RT5350_CLK_TIMER	4
+#define RT5350_CLK_WATCHDOG	5
+#define RT5350_CLK_UART		6
+#define RT5350_CLK_I2C		7
+#define RT5350_CLK_I2S		8
+#define RT5350_CLK_SPI1		9
+#define RT5350_CLK_SPI2		10
+#define RT5350_CLK_UARTLITE	11
+#define RT5350_CLK_ETHERNET	12
+#define RT5350_CLK_WMAC		13
+
+/* Ralink MT-7620 clocks */
+
+#define MT7620_CLK_XTAL		0
+#define MT7620_CLK_PLL		1
+#define MT7620_CLK_CPU		2
+#define MT7620_CLK_PERIPH	3
+#define MT7620_CLK_BUS		4
+#define MT7620_CLK_BBPPLL	5
+#define MT7620_CLK_SDHC		6
+#define MT7620_CLK_TIMER	7
+#define MT7620_CLK_WATCHDOG	8
+#define MT7620_CLK_UART		9
+#define MT7620_CLK_I2C		10
+#define MT7620_CLK_I2S		11
+#define MT7620_CLK_SPI1		12
+#define MT7620_CLK_SPI2		13
+#define MT7620_CLK_UARTLITE	14
+#define MT7620_CLK_MMC		15
+#define MT7620_CLK_WMAC		16
+
+/* Ralink MT-76X8 clocks */
+
+#define MT76X8_CLK_XTAL		0
+#define MT76X8_CLK_CPU		1
+#define MT76X8_CLK_BBPPLL	2
+#define MT76X8_CLK_PCMI2S	3
+#define MT76X8_CLK_PERIPH	4
+#define MT76X8_CLK_BUS		5
+#define MT76X8_CLK_SDHC		6
+#define MT76X8_CLK_TIMER	7
+#define MT76X8_CLK_WATCHDOG	8
+#define MT76X8_CLK_I2C		9
+#define MT76X8_CLK_I2S		10
+#define MT76X8_CLK_SPI1		11
+#define MT76X8_CLK_SPI2		12
+#define MT76X8_CLK_UART0	13
+#define MT76X8_CLK_UART1	14
+#define MT76X8_CLK_UART2	15
+#define MT76X8_CLK_MMC		16
+#define MT76X8_CLK_WMAC		17
+
+#endif /* _DT_BINDINGS_CLK_MTMIPS_H */
diff --git a/include/dt-bindings/reset/mediatek,mtmips-sysc.h b/include/dt-bindings/reset/mediatek,mtmips-sysc.h
new file mode 100644
index 000000000000..1bc6024b1f22
--- /dev/null
+++ b/include/dt-bindings/reset/mediatek,mtmips-sysc.h
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+ */
+
+#ifndef _DT_BINDINGS_RST_MTMIPS_H
+#define _DT_BINDINGS_RST_MTMIPS_H
+
+/* Ralink RT-2880 resets */
+
+#define RT2880_RST_SYS		0
+#define RT2880_RST_I2C		9
+#define RT2880_RST_FE		18
+
+/* Ralink RT-305X resets */
+
+#define RT305X_RST_SYS		0
+#define RT305X_RST_TIMER	8
+#define RT305X_RST_INTC		9
+#define RT305X_RST_MEMC		10
+#define RT305X_RST_PCM		11
+#define RT305X_RST_UART		12
+#define RT305X_RST_PIO		13
+#define RT305X_RST_DMA		14
+#define RT305X_RST_I2C		16
+#define RT305X_RST_I2S		17
+#define RT305X_RST_SPI		18
+#define RT305X_RST_UARTLITE	19
+#define RT305X_RST_WLAN		20
+#define RT305X_RST_FE		21
+#define RT305X_RST_OTG		22
+#define RT305X_RST_SW		23
+
+/* Ralink RT-3352 resets */
+
+#define RT3352_RST_SYS		0
+#define RT3352_RST_TIMER	8
+#define RT3352_RST_INTC		9
+#define RT3352_RST_MEMC		10
+#define RT3352_RST_PCM		11
+#define RT3352_RST_UART		12
+#define RT3352_RST_PIO		13
+#define RT3352_RST_DMA		14
+#define RT3352_RST_I2C		16
+#define RT3352_RST_I2S		17
+#define RT3352_RST_SPI		18
+#define RT3352_RST_UARTLITE	19
+#define RT3352_RST_WLAN		20
+#define RT3352_RST_FE		21
+#define RT3352_RST_UHST		22
+#define RT3352_RST_SW		23
+#define RT3352_RST_EPHY		24
+#define RT3352_RST_UDEV		25
+#define RT3352_RST_MIPS_CNT	28
+
+/* Ralink RT-3883 resets */
+
+#define RT3883_RST_SYS		0
+#define RT3883_RST_TIMER	8
+#define RT3883_RST_INTC		9
+#define RT3883_RST_MEMC		10
+#define RT3883_RST_PCM		11
+#define RT3883_RST_UART		12
+#define RT3883_RST_PIO		13
+#define RT3883_RST_DMA		14
+#define RT3883_RST_I2C		16
+#define RT3883_RST_I2S		17
+#define RT3883_RST_SPI		18
+#define RT3883_RST_UARTLITE	19
+#define RT3883_RST_WLAN		20
+#define RT3883_RST_FE		21
+#define RT3883_RST_UHST		22
+#define RT3883_RST_SW		23
+#define RT3883_RST_EPHY		24
+#define RT3883_RST_UDEV		25
+#define RT3883_RST_MIPS_CNT	28
+
+/* Ralink RT-5350 resets */
+
+#define RT5350_RST_SYS		0
+#define RT5350_RST_TIMER	8
+#define RT5350_RST_INTC		9
+#define RT5350_RST_MEMC		10
+#define RT5350_RST_PCM		11
+#define RT5350_RST_UART		12
+#define RT5350_RST_PIO		13
+#define RT5350_RST_DMA		14
+#define RT5350_RST_I2C		16
+#define RT5350_RST_I2S		17
+#define RT5350_RST_SPI		18
+#define RT5350_RST_UARTLITE	19
+#define RT5350_RST_WLAN		20
+#define RT5350_RST_FE		21
+#define RT5350_RST_UHST		22
+#define RT5350_RST_SW		23
+#define RT5350_RST_EPHY		24
+#define RT5350_RST_UDEV		25
+#define RT5350_RST_MIPS_CNT	28
+
+/* Ralink MT-7620 resets */
+
+#define MT7620_RST_SYS		0
+#define MT7620_RST_TIMER	8
+#define MT7620_RST_INTC		9
+#define MT7620_RST_MEMC		10
+#define MT7620_RST_PCM		11
+#define MT7620_RST_UART		12
+#define MT7620_RST_PIO		13
+#define MT7620_RST_DMA		14
+#define MT7620_RST_NAND		15
+#define MT7620_RST_I2C		16
+#define MT7620_RST_I2S		17
+#define MT7620_RST_SPI		18
+#define MT7620_RST_UARTLITE	19
+#define MT7620_RST_WLAN		20
+#define MT7620_RST_FE		21
+#define MT7620_RST_ESW		23
+#define MT7620_RST_EPHY		24
+#define MT7620_RST_UHST0	25
+#define MT7620_RST_PCIE0	26
+#define MT7620_RST_MIPS_CNT	28
+#define MT7620_RST_SDHC		30
+#define MT7620_RST_PPE		31
+
+/* Ralink MT-76X8 resets */
+
+#define MT76X8_RST_SYS		0
+#define MT76X8_RST_SPIS		3
+#define MT76X8_RST_WIFI		4
+#define MT76X8_RST_HIF		5
+#define MT76X8_RST_TIMER	8
+#define MT76X8_RST_INTC		9
+#define MT76X8_RST_MEMC		10
+#define MT76X8_RST_PCM		11
+#define MT76X8_RST_UART0	12
+#define MT76X8_RST_PIO		13
+#define MT76X8_RST_GDMA		14
+#define MT76X8_RST_I2C		16
+#define MT76X8_RST_I2S		17
+#define MT76X8_RST_SPI		18
+#define MT76X8_RST_UART1	19
+#define MT76X8_RST_UART2	20
+#define MT76X8_RST_UHST		22
+#define MT76X8_RST_ETH		23
+#define MT76X8_RST_EPHY		24
+#define MT76X8_RST_PCIE0	26
+#define MT76X8_RST_AUX_STCK	28
+#define MT76X8_RST_CRYPTO	29
+#define MT76X8_RST_SDXC		30
+#define MT76X8_RST_PWM		31
+
+#endif /* _DT_BINDINGS_RST_MTMIPS_H */
-- 
2.25.1

Re: [PATCH v2 1/6] dt-bindings: clock: add clock and reset definitions for Ralink SoCs

[Krzysztof Kozlowski]

On Sun, Jan 19, 2025 at 04:44:42PM +0100, Sergio Paracuellos wrote:
> +#endif /* _DT_BINDINGS_CLK_MTMIPS_H */
> diff --git a/include/dt-bindings/reset/mediatek,mtmips-sysc.h b/include/dt-bindings/reset/mediatek,mtmips-sysc.h
> new file mode 100644
> index 000000000000..1bc6024b1f22
> --- /dev/null
> +++ b/include/dt-bindings/reset/mediatek,mtmips-sysc.h
> @@ -0,0 +1,152 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> + */
> +
> +#ifndef _DT_BINDINGS_RST_MTMIPS_H
> +#define _DT_BINDINGS_RST_MTMIPS_H
> +
> +/* Ralink RT-2880 resets */
> +
> +#define RT2880_RST_SYS		0
> +#define RT2880_RST_I2C		9
> +#define RT2880_RST_FE		18

These do not look correct. I understood from previous discussions that
driver relies on these for its internal operation. It looks true for
clocks, but does not look true here at all. This is register bit passed
to the hardware (and I explicitly mentioned last time: that I expect
these not being register bits passed to hardware).

None of the resets are bindings - these are just hardware constants.

Best regards,
Krzysztof

Re: [PATCH v2 1/6] dt-bindings: clock: add clock and reset definitions for Ralink SoCs

[Sergio Paracuellos]

On Mon, Jan 20, 2025 at 8:45 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On Sun, Jan 19, 2025 at 04:44:42PM +0100, Sergio Paracuellos wrote:
> > +#endif /* _DT_BINDINGS_CLK_MTMIPS_H */
> > diff --git a/include/dt-bindings/reset/mediatek,mtmips-sysc.h b/include/dt-bindings/reset/mediatek,mtmips-sysc.h
> > new file mode 100644
> > index 000000000000..1bc6024b1f22
> > --- /dev/null
> > +++ b/include/dt-bindings/reset/mediatek,mtmips-sysc.h
> > @@ -0,0 +1,152 @@
> > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> > +/*
> > + * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> > + */
> > +
> > +#ifndef _DT_BINDINGS_RST_MTMIPS_H
> > +#define _DT_BINDINGS_RST_MTMIPS_H
> > +
> > +/* Ralink RT-2880 resets */
> > +
> > +#define RT2880_RST_SYS               0
> > +#define RT2880_RST_I2C               9
> > +#define RT2880_RST_FE                18
>
> These do not look correct. I understood from previous discussions that
> driver relies on these for its internal operation. It looks true for
> clocks, but does not look true here at all. This is register bit passed
> to the hardware (and I explicitly mentioned last time: that I expect
> these not being register bits passed to hardware).

I thought you were referring to reg addresses and interrupts since
there was no comment in the reset part in v1. Anyway, it is clear now,
thanks.

>
> None of the resets are bindings - these are just hardware constants.

Understood. Will drop this file and update dts.

>
> Best regards,
> Krzysztof

Thanks,
    Sergio Paracuellos

[PATCH v2 2/6] mips: dts: ralink: rt2880: update system controller node and its consumers

[Sergio Paracuellos]

Current RT2880 device tree file system controller node is wrong since it is
not matching bindings. Hence, update it to match current bindings updating
it also to use new introduced clock constants.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 arch/mips/boot/dts/ralink/rt2880.dtsi | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/mips/boot/dts/ralink/rt2880.dtsi b/arch/mips/boot/dts/ralink/rt2880.dtsi
index 8fc1987d9063..1f2ea3434324 100644
--- a/arch/mips/boot/dts/ralink/rt2880.dtsi
+++ b/arch/mips/boot/dts/ralink/rt2880.dtsi
@@ -1,4 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
+
 / {
 	#address-cells = <1>;
 	#size-cells = <1>;
@@ -25,9 +27,11 @@ palmbus@300000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		sysc@0 {
-			compatible = "ralink,rt2880-sysc";
+		sysc: syscon@0 {
+			compatible = "ralink,rt2880-sysc", "syscon";
 			reg = <0x0 0x100>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		intc: intc@200 {
@@ -50,6 +54,8 @@ uartlite@c00 {
 			compatible = "ralink,rt2880-uart", "ns16550a";
 			reg = <0xc00 0x100>;
 
+			clocks = <&sysc RT2880_CLK_UARTLITE>;
+
 			interrupt-parent = <&intc>;
 			interrupts = <8>;
 
-- 
2.25.1

[PATCH v2 3/6] mips: dts: ralink: rt3050: update system controller node and its consumers

[Sergio Paracuellos]

Current RT3050 device tree file system controller node is wrong since it is
not matching bindings. Hence, update it to match current bindings updating
it also to use new introduced clock constants.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 arch/mips/boot/dts/ralink/rt3050.dtsi | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/mips/boot/dts/ralink/rt3050.dtsi b/arch/mips/boot/dts/ralink/rt3050.dtsi
index 23062333a76d..a7d9bb9bc1af 100644
--- a/arch/mips/boot/dts/ralink/rt3050.dtsi
+++ b/arch/mips/boot/dts/ralink/rt3050.dtsi
@@ -1,4 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
+
 / {
 	#address-cells = <1>;
 	#size-cells = <1>;
@@ -25,9 +27,11 @@ palmbus@10000000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		sysc@0 {
-			compatible = "ralink,rt3052-sysc", "ralink,rt3050-sysc";
+		sysc: syscon@0 {
+			compatible = "ralink,rt3052-sysc", "ralink,rt3050-sysc", "syscon";
 			reg = <0x0 0x100>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		intc: intc@200 {
@@ -50,6 +54,8 @@ uartlite@c00 {
 			compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
 			reg = <0xc00 0x100>;
 
+			clocks = <&sysc RT305X_CLK_UARTLITE>;
+
 			interrupt-parent = <&intc>;
 			interrupts = <12>;
 
-- 
2.25.1

[PATCH v2 4/6] mips: dts: ralink: rt3883: update system controller node and its consumers

[Sergio Paracuellos]

Current RT3883 device tree file system controller node is wrong since it is
not matching bindings. Hence, update it to match current bindings updating
it also to use new introduced clock constants.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 arch/mips/boot/dts/ralink/rt3883.dtsi | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/mips/boot/dts/ralink/rt3883.dtsi b/arch/mips/boot/dts/ralink/rt3883.dtsi
index 61132cf157e5..11d111a06037 100644
--- a/arch/mips/boot/dts/ralink/rt3883.dtsi
+++ b/arch/mips/boot/dts/ralink/rt3883.dtsi
@@ -1,4 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
+
 / {
 	#address-cells = <1>;
 	#size-cells = <1>;
@@ -25,9 +27,11 @@ palmbus@10000000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		sysc@0 {
-			compatible = "ralink,rt3883-sysc", "ralink,rt3050-sysc";
+		sysc: syscon@0 {
+			compatible = "ralink,rt3883-sysc", "syscon";
 			reg = <0x0 0x100>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		intc: intc@200 {
@@ -50,6 +54,8 @@ uartlite@c00 {
 			compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
 			reg = <0xc00 0x100>;
 
+			clocks = <&sysc RT3883_CLK_UARTLITE>;
+
 			interrupt-parent = <&intc>;
 			interrupts = <12>;
 
-- 
2.25.1

[PATCH v2 5/6] mips: dts: ralink: mt7620a: update system controller node and its consumers

[Sergio Paracuellos]

Current MT7620A device tree file system controller node is wrong since it is
not matching bindings. Hence, update it to match current bindings updating
it also to use new introduced clock constants.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 arch/mips/boot/dts/ralink/mt7620a.dtsi | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/mips/boot/dts/ralink/mt7620a.dtsi b/arch/mips/boot/dts/ralink/mt7620a.dtsi
index 1f6e5320f486..d66045948a83 100644
--- a/arch/mips/boot/dts/ralink/mt7620a.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7620a.dtsi
@@ -1,4 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
+
 / {
 	#address-cells = <1>;
 	#size-cells = <1>;
@@ -25,9 +27,11 @@ palmbus@10000000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		sysc@0 {
-			compatible = "ralink,mt7620a-sysc";
+		sysc: syscon@0 {
+			compatible = "ralink,mt7620-sysc", "syscon";
 			reg = <0x0 0x100>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		intc: intc@200 {
@@ -50,6 +54,8 @@ uartlite@c00 {
 			compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
 			reg = <0xc00 0x100>;
 
+			clocks = <&sysc MT7620_CLK_UARTLITE>;
+
 			interrupt-parent = <&intc>;
 			interrupts = <12>;
 
-- 
2.25.1

[PATCH v2 6/6] mips: dts: ralink: mt7628a: update system controller node and its consumers

[Sergio Paracuellos]

Current MT7628A device tree file system controller node is wrong since it is
not matching bindings. Hence, update it to match current bindings updating
it also to use new introduced clock and reset constants.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 arch/mips/boot/dts/ralink/mt7628a.dtsi | 43 ++++++++++++++++----------
 1 file changed, 27 insertions(+), 16 deletions(-)

diff --git a/arch/mips/boot/dts/ralink/mt7628a.dtsi b/arch/mips/boot/dts/ralink/mt7628a.dtsi
index 45a15e005cc4..bc69866e2134 100644
--- a/arch/mips/boot/dts/ralink/mt7628a.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7628a.dtsi
@@ -1,4 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
+#include <dt-bindings/reset/mediatek,mtmips-sysc.h>
 
 / {
 	#address-cells = <1>;
@@ -16,11 +18,6 @@ cpu@0 {
 		};
 	};
 
-	resetc: reset-controller {
-		compatible = "ralink,rt2880-reset";
-		#reset-cells = <1>;
-	};
-
 	cpuintc: interrupt-controller {
 		#address-cells = <0>;
 		#interrupt-cells = <1>;
@@ -36,9 +33,11 @@ palmbus@10000000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		sysc: system-controller@0 {
-			compatible = "ralink,mt7620a-sysc", "syscon";
+		sysc: syscon@0 {
+			compatible = "ralink,mt7628-sysc", "syscon";
 			reg = <0x0 0x60>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		pinmux: pinmux@60 {
@@ -138,7 +137,7 @@ watchdog: watchdog@100 {
 			compatible = "mediatek,mt7621-wdt";
 			reg = <0x100 0x30>;
 
-			resets = <&resetc 8>;
+			resets = <&sysc MT76X8_RST_TIMER>;
 			reset-names = "wdt";
 
 			interrupt-parent = <&intc>;
@@ -154,7 +153,7 @@ intc: interrupt-controller@200 {
 			interrupt-controller;
 			#interrupt-cells = <1>;
 
-			resets = <&resetc 9>;
+			resets = <&sysc MT76X8_RST_INTC>;
 			reset-names = "intc";
 
 			interrupt-parent = <&cpuintc>;
@@ -190,7 +189,9 @@ spi: spi@b00 {
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinmux_spi_spi>;
 
-			resets = <&resetc 18>;
+			clocks = <&sysc MT76X8_CLK_SPI1>;
+
+			resets = <&sysc MT76X8_RST_SPI>;
 			reset-names = "spi";
 
 			#address-cells = <1>;
@@ -206,7 +207,9 @@ i2c: i2c@900 {
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinmux_i2c_i2c>;
 
-			resets = <&resetc 16>;
+			clocks = <&sysc MT76X8_CLK_I2C>;
+
+			resets = <&sysc MT76X8_RST_I2C>;
 			reset-names = "i2c";
 
 			#address-cells = <1>;
@@ -222,7 +225,9 @@ uart0: uartlite@c00 {
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinmux_uart0_uart>;
 
-			resets = <&resetc 12>;
+			clocks = <&sysc MT76X8_CLK_UART0>;
+
+			resets = <&sysc MT76X8_RST_UART0>;
 			reset-names = "uart0";
 
 			interrupt-parent = <&intc>;
@@ -238,7 +243,9 @@ uart1: uart1@d00 {
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinmux_uart1_uart>;
 
-			resets = <&resetc 19>;
+			clocks = <&sysc MT76X8_CLK_UART1>;
+
+			resets = <&sysc MT76X8_RST_UART1>;
 			reset-names = "uart1";
 
 			interrupt-parent = <&intc>;
@@ -254,7 +261,9 @@ uart2: uart2@e00 {
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinmux_uart2_uart>;
 
-			resets = <&resetc 20>;
+			clocks = <&sysc MT76X8_CLK_UART2>;
+
+			resets = <&sysc MT76X8_RST_UART2>;
 			reset-names = "uart2";
 
 			interrupt-parent = <&intc>;
@@ -271,8 +280,8 @@ usb_phy: usb-phy@10120000 {
 		#phy-cells = <0>;
 
 		ralink,sysctl = <&sysc>;
-		resets = <&resetc 22 &resetc 25>;
-		reset-names = "host", "device";
+		resets = <&sysc MT76X8_RST_UHST>;
+		reset-names = "host";
 	};
 
 	usb@101c0000 {
@@ -290,6 +299,8 @@ wmac: wmac@10300000 {
 		compatible = "mediatek,mt7628-wmac";
 		reg = <0x10300000 0x100000>;
 
+		clocks = <&sysc MT76X8_CLK_WMAC>;
+
 		interrupt-parent = <&cpuintc>;
 		interrupts = <6>;
 
-- 
2.25.1