From: Jiwei Sun <sjiwei@163.com>
To: macro@orcam.me.uk, ilpo.jarvinen@linux.intel.com, bhelgaas@google.com
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
helgaas@kernel.org, lukas@wunner.de, ahuang12@lenovo.com,
sunjw10@lenovo.com, jiwei.sun.bj@qq.com, sunjw10@outlook.com
Subject: [PATCH v4 0/2] PCI: Fix the issue of failed speed limit lifting
Date: Thu, 23 Jan 2025 13:51:53 +0800 [thread overview]
Message-ID: <20250123055155.22648-1-sjiwei@163.com> (raw)
From: Jiwei Sun <sunjw10@lenovo.com>
Since commit de9a6c8d5dbf ("PCI/bwctrl: Add pcie_set_target_speed() to set
PCIe Link Speed"), there are two potential issues in the function
pcie_failed_link_retrain().
(1) The macro PCIE_LNKCTL2_TLS2SPEED() and PCIE_LNKCAP_SLS2SPEED() just
use the link speed field of the registers. However, there are many other
different function fields in the Link Control 2 Register or the Link
Capabilities Register. If the register value is directly used by the two
macros, it may cause getting an error link speed value (PCI_SPEED_UNKNOWN).
(2) In the pcie_failed_link_retrain(), the local variable lnkctl2 is not
changed after reading from PCI_EXP_LNKCTL2. It might cause that the
removing 2.5GT/s downstream link speed restriction codes are not executed.
In order to avoid the above-mentioned potential issues, only keep link
speed field of the two registers before using and reread the Link Control 2
Register before using.
This series focuses on the first patch of the original series [1]. The
second one of the original series will submitted via the other single
patch.
[1] https://lore.kernel.org/linux-pci/tencent_DD9CBE5B44210B43A04EF8DAF52506A08509@qq.com/
---
v4 changes:
- rename the variable name in the macro
v3 changes:
- add fix tag in the commit messages of first patch
- add an empty line after the local variable definition in the macro
- adjust the position of reading the Link Control 2 register in the code
v2 changes:
- divide the two issues into different patches
- get fixed inside the macros
Jiwei Sun (2):
PCI: Fix the wrong reading of register fields
PCI: Adjust the position of reading the Link Control 2 register
drivers/pci/pci.h | 32 +++++++++++++++++++-------------
drivers/pci/quirks.c | 6 ++++--
2 files changed, 23 insertions(+), 15 deletions(-)
--
2.34.1
next reply other threads:[~2025-01-23 5:52 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-23 5:51 Jiwei Sun [this message]
2025-01-23 5:51 ` [PATCH v4 1/2] PCI: Fix the wrong reading of register fields Jiwei Sun
2025-01-23 5:51 ` [PATCH v4 2/2] PCI: Adjust the position of reading the Link Control 2 register Jiwei Sun
2025-02-26 12:20 ` [PATCH v4 0/2] PCI: Fix the issue of failed speed limit lifting Jiwei Sun
2025-06-24 20:54 ` Bjorn Helgaas
2025-06-24 22:07 ` Maciej W. Rozycki
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