From: Mark Brown <broonie@kernel.org>
To: Marc Zyngier <maz@kernel.org>,
Oliver Upton <oliver.upton@linux.dev>,
Joey Gouly <joey.gouly@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Will Deacon <will@kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Jonathan Corbet <corbet@lwn.net>, Shuah Khan <shuah@kernel.org>
Cc: Dave Martin <Dave.Martin@arm.com>, Fuad Tabba <tabba@google.com>,
Mark Rutland <mark.rutland@arm.com>,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org,
Mark Brown <broonie@kernel.org>
Subject: [PATCH v4 23/27] KVM: arm64: Handle SME exceptions
Date: Fri, 14 Feb 2025 01:58:06 +0000 [thread overview]
Message-ID: <20250214-kvm-arm64-sme-v4-23-d64a681adcc2@kernel.org> (raw)
In-Reply-To: <20250214-kvm-arm64-sme-v4-0-d64a681adcc2@kernel.org>
The access control for SME follows the same structure as for the base FP
and SVE extensions, with control being via CPACR_ELx.SMEN and CPTR_EL2.TSM
mirroring the equivalent FPSIMD and SVE controls in those registers. Add
handling for these controls and exceptions mirroring the existing handling
for FPSIMD and SVE.
When the hardware is in streaming mode guest operations that are invalid in
in streaming mode will generate SME exceptions. Since these exceptions may
be routed to EL1 with no opportunity for the hypervisor to intercept them
we already have code which ensures that we exit streaming mode before
running the guest. This ensures that guests do not receive unexpected
SME exceptions.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/kvm/handle_exit.c | 14 ++++++++++++++
arch/arm64/kvm/hyp/nvhe/switch.c | 11 ++++++-----
arch/arm64/kvm/hyp/vhe/switch.c | 21 ++++++++++++++++-----
3 files changed, 36 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c
index 512d152233ff20eb6c65abbf731b4bcb543a7d07..036e722a8f3ce03f0bd756a84a6fbffeae9bf359 100644
--- a/arch/arm64/kvm/handle_exit.c
+++ b/arch/arm64/kvm/handle_exit.c
@@ -227,6 +227,19 @@ static int handle_sve(struct kvm_vcpu *vcpu)
return 1;
}
+/*
+ * Guest access to SME registers should be routed to this handler only
+ * when the system doesn't support SME.
+ */
+static int handle_sme(struct kvm_vcpu *vcpu)
+{
+ if (guest_hyp_sme_traps_enabled(vcpu))
+ return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu));
+
+ kvm_inject_undefined(vcpu);
+ return 1;
+}
+
/*
* Two possibilities to handle a trapping ptrauth instruction:
*
@@ -310,6 +323,7 @@ static exit_handle_fn arm_exit_handlers[] = {
[ESR_ELx_EC_SVC64] = handle_svc,
[ESR_ELx_EC_SYS64] = kvm_handle_sys_reg,
[ESR_ELx_EC_SVE] = handle_sve,
+ [ESR_ELx_EC_SME] = handle_sme,
[ESR_ELx_EC_ERET] = kvm_handle_eret,
[ESR_ELx_EC_IABT_LOW] = kvm_handle_guest_abort,
[ESR_ELx_EC_DABT_LOW] = kvm_handle_guest_abort,
diff --git a/arch/arm64/kvm/hyp/nvhe/switch.c b/arch/arm64/kvm/hyp/nvhe/switch.c
index eaeda9c8a1aa62f8f7eed36dbedc74513a453e4e..1f1883bc6f0cc270dd1ad38f96b9a0048e238e72 100644
--- a/arch/arm64/kvm/hyp/nvhe/switch.c
+++ b/arch/arm64/kvm/hyp/nvhe/switch.c
@@ -49,17 +49,16 @@ static void __activate_cptr_traps(struct kvm_vcpu *vcpu)
val |= CPACR_EL1_FPEN;
if (vcpu_has_sve(vcpu))
val |= CPACR_EL1_ZEN;
+ if (vcpu_has_sme(vcpu))
+ val |= CPACR_EL1_SMEN;
}
write_sysreg(val, cpacr_el1);
} else {
val |= CPTR_EL2_TTA | CPTR_NVHE_EL2_RES1;
- /*
- * Always trap SME since it's not supported in KVM.
- * TSM is RES1 if SME isn't implemented.
- */
- val |= CPTR_EL2_TSM;
+ if (!vcpu_has_sme(vcpu) || !guest_owns_fp_regs())
+ val |= CPTR_EL2_TSM;
if (!vcpu_has_sve(vcpu) || !guest_owns_fp_regs())
val |= CPTR_EL2_TZ;
@@ -222,6 +221,7 @@ static const exit_handler_fn hyp_exit_handlers[] = {
[ESR_ELx_EC_CP15_32] = kvm_hyp_handle_cp15_32,
[ESR_ELx_EC_SYS64] = kvm_hyp_handle_sysreg,
[ESR_ELx_EC_SVE] = kvm_hyp_handle_fpsimd,
+ [ESR_ELx_EC_SME] = kvm_hyp_handle_fpsimd,
[ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd,
[ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low,
[ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low,
@@ -233,6 +233,7 @@ static const exit_handler_fn pvm_exit_handlers[] = {
[0 ... ESR_ELx_EC_MAX] = NULL,
[ESR_ELx_EC_SYS64] = kvm_handle_pvm_sys64,
[ESR_ELx_EC_SVE] = kvm_handle_pvm_restricted,
+ [ESR_ELx_EC_SME] = kvm_handle_pvm_restricted,
[ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd,
[ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low,
[ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low,
diff --git a/arch/arm64/kvm/hyp/vhe/switch.c b/arch/arm64/kvm/hyp/vhe/switch.c
index 647737d6e8d0b5f41b2a8d25a06265e4703126b3..44e3f0577ceea2a1574038c97fd769fef30d7098 100644
--- a/arch/arm64/kvm/hyp/vhe/switch.c
+++ b/arch/arm64/kvm/hyp/vhe/switch.c
@@ -83,6 +83,8 @@ static void __activate_cptr_traps(struct kvm_vcpu *vcpu)
val |= CPACR_EL1_FPEN;
if (vcpu_has_sve(vcpu))
val |= CPACR_EL1_ZEN;
+ if (vcpu_has_sme(vcpu))
+ val |= CPACR_EL1_SMEN;
} else {
__activate_traps_fpsimd32(vcpu);
}
@@ -126,6 +128,8 @@ static void __activate_cptr_traps(struct kvm_vcpu *vcpu)
val &= ~CPACR_EL1_FPEN;
if (!(SYS_FIELD_GET(CPACR_EL1, ZEN, cptr) & BIT(0)))
val &= ~CPACR_EL1_ZEN;
+ if (!(SYS_FIELD_GET(CPACR_EL1, SMEN, cptr) & BIT(0)))
+ val &= ~CPACR_EL1_SMEN;
if (kvm_has_feat(vcpu->kvm, ID_AA64MMFR3_EL1, S2POE, IMP))
val |= cptr & CPACR_EL1_E0POE;
@@ -486,22 +490,28 @@ static bool kvm_hyp_handle_cpacr_el1(struct kvm_vcpu *vcpu, u64 *exit_code)
return true;
}
-static bool kvm_hyp_handle_zcr_el2(struct kvm_vcpu *vcpu, u64 *exit_code)
+static bool kvm_hyp_handle_vec_cr_el2(struct kvm_vcpu *vcpu, u64 *exit_code)
{
u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
if (!vcpu_has_nv(vcpu))
return false;
- if (sysreg != SYS_ZCR_EL2)
+ switch (sysreg) {
+ case SYS_ZCR_EL2:
+ case SYS_SMCR_EL2:
+ break;
+ default:
return false;
+ }
if (guest_owns_fp_regs())
return false;
/*
- * ZCR_EL2 traps are handled in the slow path, with the expectation
- * that the guest's FP context has already been loaded onto the CPU.
+ * ZCR_EL2 and SMCR_EL2 traps are handled in the slow path,
+ * with the expectation that the guest's FP context has
+ * already been loaded onto the CPU.
*
* Load the guest's FP context and unconditionally forward to the
* slow path for handling (i.e. return false).
@@ -521,7 +531,7 @@ static bool kvm_hyp_handle_sysreg_vhe(struct kvm_vcpu *vcpu, u64 *exit_code)
if (kvm_hyp_handle_cpacr_el1(vcpu, exit_code))
return true;
- if (kvm_hyp_handle_zcr_el2(vcpu, exit_code))
+ if (kvm_hyp_handle_vec_cr_el2(vcpu, exit_code))
return true;
return kvm_hyp_handle_sysreg(vcpu, exit_code);
@@ -531,6 +541,7 @@ static const exit_handler_fn hyp_exit_handlers[] = {
[0 ... ESR_ELx_EC_MAX] = NULL,
[ESR_ELx_EC_CP15_32] = kvm_hyp_handle_cp15_32,
[ESR_ELx_EC_SYS64] = kvm_hyp_handle_sysreg_vhe,
+ [ESR_ELx_EC_SME] = kvm_hyp_handle_fpsimd,
[ESR_ELx_EC_SVE] = kvm_hyp_handle_fpsimd,
[ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd,
[ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low,
--
2.39.5
next prev parent reply other threads:[~2025-02-14 2:02 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-14 1:57 [PATCH v4 00/27] KVM: arm64: Implement support for SME in non-protected guests Mark Brown
2025-02-14 1:57 ` [PATCH v4 01/27] arm64/fpsimd: Update FA64 and ZT0 enables when loading SME state Mark Brown
2025-02-14 1:57 ` [PATCH v4 02/27] arm64/fpsimd: Decide to save ZT0 and streaming mode FFR at bind time Mark Brown
2025-02-14 1:57 ` [PATCH v4 03/27] arm64/fpsimd: Check enable bit for FA64 when saving EFI state Mark Brown
2025-02-14 1:57 ` [PATCH v4 04/27] arm64/fpsimd: Determine maximum virtualisable SME vector length Mark Brown
2025-02-14 1:57 ` [PATCH v4 05/27] KVM: arm64: Introduce non-UNDEF FGT control Mark Brown
2025-02-14 1:57 ` [PATCH v4 06/27] KVM: arm64: Pay attention to FFR parameter in SVE save and load Mark Brown
2025-02-14 1:57 ` [PATCH v4 07/27] KVM: arm64: Pull ctxt_has_ helpers to start of sysreg-sr.h Mark Brown
2025-02-14 1:57 ` [PATCH v4 08/27] KVM: arm64: Move SVE state access macros after feature test macros Mark Brown
2025-02-14 1:57 ` [PATCH v4 09/27] KVM: arm64: Rename SVE finalization constants to be more general Mark Brown
2025-02-14 1:57 ` [PATCH v4 10/27] KVM: arm64: Document the KVM ABI for SME Mark Brown
2025-02-14 1:57 ` [PATCH v4 11/27] KVM: arm64: Define internal features " Mark Brown
2025-02-14 1:57 ` [PATCH v4 12/27] KVM: arm64: Rename sve_state_reg_region Mark Brown
2025-02-14 1:57 ` [PATCH v4 13/27] KVM: arm64: Store vector lengths in an array Mark Brown
2025-02-14 1:57 ` [PATCH v4 14/27] KVM: arm64: Implement SME vector length configuration Mark Brown
2025-02-14 1:57 ` [PATCH v4 15/27] KVM: arm64: Support SME control registers Mark Brown
2025-02-14 1:57 ` [PATCH v4 16/27] KVM: arm64: Support TPIDR2_EL0 Mark Brown
2025-02-14 1:58 ` [PATCH v4 17/27] KVM: arm64: Support SME identification registers for guests Mark Brown
2025-02-14 1:58 ` [PATCH v4 18/27] KVM: arm64: Support SME priority registers Mark Brown
2025-02-14 1:58 ` [PATCH v4 19/27] KVM: arm64: Provide assembly for SME state restore Mark Brown
2025-02-14 1:58 ` [PATCH v4 20/27] KVM: arm64: Support userspace access to streaming mode Z and P registers Mark Brown
2025-02-14 1:58 ` [PATCH v4 21/27] KVM: arm64: Expose SME specific state to userspace Mark Brown
2025-02-14 1:58 ` [PATCH v4 22/27] KVM: arm64: Context switch SME state for normal guests Mark Brown
2025-02-14 1:58 ` Mark Brown [this message]
2025-02-14 1:58 ` [PATCH v4 24/27] KVM: arm64: Expose SME to nested guests Mark Brown
2025-02-14 1:58 ` [PATCH v4 25/27] KVM: arm64: Provide interface for configuring and enabling SME for guests Mark Brown
2025-02-14 1:58 ` [PATCH v4 26/27] KVM: arm64: selftests: Add SME system registers to get-reg-list Mark Brown
2025-02-14 1:58 ` [PATCH v4 27/27] KVM: arm64: selftests: Add SME to set_id_regs test Mark Brown
2025-02-14 9:24 ` [PATCH v4 00/27] KVM: arm64: Implement support for SME in non-protected guests Marc Zyngier
2025-02-14 15:13 ` Mark Brown
2025-02-17 9:37 ` Marc Zyngier
2025-02-18 22:54 ` Mark Brown
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