From: Borislav Petkov <bp@alien8.de>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Komal Bajaj <quic_kbajaj@quicinc.com>,
tony.luck@intel.com, james.morse@arm.com, mchehab@kernel.org,
rric@kernel.org, andy.gross@linaro.org, vnkgutta@codeaurora.org,
linux-arm-msm@vger.kernel.org, linux-edac@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] qcom: llcc/edac: Correct interrupt enable register configuration
Date: Fri, 14 Feb 2025 20:45:02 +0100 [thread overview]
Message-ID: <20250214194502.GAZ6-dPgSc-QEEdufv@fat_crate.local> (raw)
In-Reply-To: <20250214131840.desyshjr3dbb5lyl@thinkpad>
On Fri, Feb 14, 2025 at 06:48:40PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Nov 19, 2024 at 12:16:08PM +0530, Komal Bajaj wrote:
> > The previous implementation incorrectly configured the cmn_interrupt_2_enable
> > register for interrupt handling. Using cmn_interrupt_2_enable to configure Tag,
> > Data RAM ECC interrupts would lead to issues like double handling of the
> > interrupts (EL1 and EL3) as cmn_interrupt_2_enable is meant to be configured
> > for interrupts which needs to be handled by EL3.
> >
> > EL1 LLCC EDAC driver needs to use cmn_interrupt_0_enable register to
> > configure Tag, Data RAM ECC interrupts instead of cmn_interrupt_2_enable.
> >
>
> Cc: stable@vger.kernel.org
>
> > Fixes: 27450653f1db ("drivers: edac: Add EDAC driver support for QCOM SoCs")
> > Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Applied, thanks.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
prev parent reply other threads:[~2025-02-14 19:45 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-19 6:46 Komal Bajaj
2024-11-20 11:59 ` Dmitry Baryshkov
2024-12-05 10:29 ` Komal Bajaj
2025-02-14 8:30 ` Komal Bajaj
2025-02-14 13:18 ` Manivannan Sadhasivam
2025-02-14 19:45 ` Borislav Petkov [this message]
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