* [PATCH v2 0/3] Add Rockchip 3568001/2 errata workarounds and enable ITS on RK356x
@ 2025-02-16 22:16 Dmitry Osipenko
2025-02-16 22:16 ` [PATCH v2 1/3] irqchip/gic-v3: Add Rockchip 3568002 erratum workaround Dmitry Osipenko
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Dmitry Osipenko @ 2025-02-16 22:16 UTC (permalink / raw)
To: Heiko Stuebner, Marc Zyngier
Cc: Rob Herring, Krzysztof Kozlowski, Thomas Gleixner, devicetree,
linux-rockchip, linux-kernel, Kever Yang, XiaoDong Huang,
Peter Geis, Robin Murphy, kernel
Enable GIC ITS support on Rockchip RK3566/RK3568 SoCs by adding
necessary GIC erratum workarounds and moving RK356x PCIe MSI to use
ITS instead of MBI.
Changelog:
v2: - Changed Kconfig and commit descriptions of the GIC driver patch,
as was requested by Marc Zyngier.
- Added ack from Marc Zyngier to the GIC driver patch.
- Squashed DT patch that added dma-noncoherent property to GIC node
into the patch that adds MSI controller node, as was suggested by
Marc Zyngier.
Dmitry Osipenko (3):
irqchip/gic-v3: Add Rockchip 3568002 erratum workaround
arm64: dts: rockchip: rk356x: Add MSI controller node
arm64: dts: rockchip: rk356x: Move PCIe MSI to use GIC ITS instead of
MBI
Documentation/arch/arm64/silicon-errata.rst | 2 ++
arch/arm64/Kconfig | 9 ++++++++
arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 14 ++++++++++-
drivers/irqchip/irq-gic-v3-its.c | 23 ++++++++++++++++++-
4 files changed, 46 insertions(+), 2 deletions(-)
--
2.48.1
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v2 1/3] irqchip/gic-v3: Add Rockchip 3568002 erratum workaround 2025-02-16 22:16 [PATCH v2 0/3] Add Rockchip 3568001/2 errata workarounds and enable ITS on RK356x Dmitry Osipenko @ 2025-02-16 22:16 ` Dmitry Osipenko 2025-02-21 9:01 ` [tip: irq/drivers] " tip-bot2 for Dmitry Osipenko 2025-02-16 22:16 ` [PATCH v2 2/3] arm64: dts: rockchip: rk356x: Add MSI controller node Dmitry Osipenko 2025-02-16 22:16 ` [PATCH v2 3/3] arm64: dts: rockchip: rk356x: Move PCIe MSI to use GIC ITS instead of MBI Dmitry Osipenko 2 siblings, 1 reply; 7+ messages in thread From: Dmitry Osipenko @ 2025-02-16 22:16 UTC (permalink / raw) To: Heiko Stuebner, Marc Zyngier Cc: Rob Herring, Krzysztof Kozlowski, Thomas Gleixner, devicetree, linux-rockchip, linux-kernel, Kever Yang, XiaoDong Huang, Peter Geis, Robin Murphy, kernel Rockchip RK3566/RK3568 GIC600 integration has DDR addressing limited to the first 32bit of physical address space. Rockchip assigned Erratum ID #3568002 for this issue. Add driver quirk for this Rockchip GIC Erratum. Note, that the 0x0201743b GIC600 ID is not Rockchip-specific and is common for many ARM GICv3 implementations. Hence, there is an extra of_machine_is_compatible() check. Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> --- Documentation/arch/arm64/silicon-errata.rst | 2 ++ arch/arm64/Kconfig | 9 ++++++++ drivers/irqchip/irq-gic-v3-its.c | 23 ++++++++++++++++++++- 3 files changed, 33 insertions(+), 1 deletion(-) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst index f074f6219f5c..f968c13b46a7 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -284,6 +284,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | Rockchip | RK3588 | #3588001 | ROCKCHIP_ERRATUM_3588001 | +----------------+-----------------+-----------------+-----------------------------+ +| Rockchip | RK3568 | #3568002 | ROCKCHIP_ERRATUM_3568002 | ++----------------+-----------------+-----------------+-----------------------------+ +----------------+-----------------+-----------------+-----------------------------+ | Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 | +----------------+-----------------+-----------------+-----------------------------+ diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index c997b27b7da1..3619eca185f9 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1302,6 +1302,15 @@ config NVIDIA_CARMEL_CNP_ERRATUM If unsure, say Y. +config ROCKCHIP_ERRATUM_3568002 + bool "Rockchip 3568002: GIC600 can not access physical addresses higher than 4GB" + default y + help + The Rockchip RK3566 and RK3568 GIC600 SoC integrations have AXI + addressing limited to the first 32bit of physical address space. + + If unsure, say Y. + config ROCKCHIP_ERRATUM_3588001 bool "Rockchip 3588001: GIC600 can not support shareability attributes" default y diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 8c3ec5734f1e..f30ed281882f 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -205,13 +205,15 @@ static DEFINE_IDA(its_vpeid_ida); #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) #define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K) +static gfp_t gfp_flags_quirk; + static struct page *its_alloc_pages_node(int node, gfp_t gfp, unsigned int order) { struct page *page; int ret = 0; - page = alloc_pages_node(node, gfp, order); + page = alloc_pages_node(node, gfp | gfp_flags_quirk, order); if (!page) return NULL; @@ -4887,6 +4889,17 @@ static bool __maybe_unused its_enable_quirk_hip09_162100801(void *data) return true; } +static bool __maybe_unused its_enable_rk3568002(void *data) +{ + if (!of_machine_is_compatible("rockchip,rk3566") && + !of_machine_is_compatible("rockchip,rk3568")) + return false; + + gfp_flags_quirk |= GFP_DMA32; + + return true; +} + static const struct gic_quirk its_quirks[] = { #ifdef CONFIG_CAVIUM_ERRATUM_22375 { @@ -4954,6 +4967,14 @@ static const struct gic_quirk its_quirks[] = { .property = "dma-noncoherent", .init = its_set_non_coherent, }, +#ifdef CONFIG_ROCKCHIP_ERRATUM_3568002 + { + .desc = "ITS: Rockchip erratum RK3568002", + .iidr = 0x0201743b, + .mask = 0xffffffff, + .init = its_enable_rk3568002, + }, +#endif { } }; -- 2.48.1 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [tip: irq/drivers] irqchip/gic-v3: Add Rockchip 3568002 erratum workaround 2025-02-16 22:16 ` [PATCH v2 1/3] irqchip/gic-v3: Add Rockchip 3568002 erratum workaround Dmitry Osipenko @ 2025-02-21 9:01 ` tip-bot2 for Dmitry Osipenko 0 siblings, 0 replies; 7+ messages in thread From: tip-bot2 for Dmitry Osipenko @ 2025-02-21 9:01 UTC (permalink / raw) To: linux-tip-commits Cc: Dmitry Osipenko, Thomas Gleixner, Marc Zyngier, x86, linux-kernel The following commit has been merged into the irq/drivers branch of tip: Commit-ID: 2d81e1bb625238d40a686ed909ff3e1abab7556a Gitweb: https://git.kernel.org/tip/2d81e1bb625238d40a686ed909ff3e1abab7556a Author: Dmitry Osipenko <dmitry.osipenko@collabora.com> AuthorDate: Mon, 17 Feb 2025 01:16:32 +03:00 Committer: Thomas Gleixner <tglx@linutronix.de> CommitterDate: Fri, 21 Feb 2025 09:58:07 +01:00 irqchip/gic-v3: Add Rockchip 3568002 erratum workaround Rockchip RK3566/RK3568 GIC600 integration has DDR addressing limited to the first 32bit of physical address space. Rockchip assigned Erratum ID #3568002 for this issue. Add driver quirk for this Rockchip GIC Erratum. Note, that the 0x0201743b GIC600 ID is not Rockchip-specific and is common for many ARM GICv3 implementations. Hence, there is an extra of_machine_is_compatible() check. Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/all/20250216221634.364158-2-dmitry.osipenko@collabora.com --- Documentation/arch/arm64/silicon-errata.rst | 2 ++- arch/arm64/Kconfig | 9 ++++++++- drivers/irqchip/irq-gic-v3-its.c | 23 +++++++++++++++++++- 3 files changed, 33 insertions(+), 1 deletion(-) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst index f074f62..f968c13 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -284,6 +284,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | Rockchip | RK3588 | #3588001 | ROCKCHIP_ERRATUM_3588001 | +----------------+-----------------+-----------------+-----------------------------+ +| Rockchip | RK3568 | #3568002 | ROCKCHIP_ERRATUM_3568002 | ++----------------+-----------------+-----------------+-----------------------------+ +----------------+-----------------+-----------------+-----------------------------+ | Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 | +----------------+-----------------+-----------------+-----------------------------+ diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index fcdd0ed..0507e47 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1303,6 +1303,15 @@ config NVIDIA_CARMEL_CNP_ERRATUM If unsure, say Y. +config ROCKCHIP_ERRATUM_3568002 + bool "Rockchip 3568002: GIC600 can not access physical addresses higher than 4GB" + default y + help + The Rockchip RK3566 and RK3568 GIC600 SoC integrations have AXI + addressing limited to the first 32bit of physical address space. + + If unsure, say Y. + config ROCKCHIP_ERRATUM_3588001 bool "Rockchip 3588001: GIC600 can not support shareability attributes" default y diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 8c3ec57..f30ed28 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -205,13 +205,15 @@ static DEFINE_IDA(its_vpeid_ida); #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) #define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K) +static gfp_t gfp_flags_quirk; + static struct page *its_alloc_pages_node(int node, gfp_t gfp, unsigned int order) { struct page *page; int ret = 0; - page = alloc_pages_node(node, gfp, order); + page = alloc_pages_node(node, gfp | gfp_flags_quirk, order); if (!page) return NULL; @@ -4887,6 +4889,17 @@ static bool __maybe_unused its_enable_quirk_hip09_162100801(void *data) return true; } +static bool __maybe_unused its_enable_rk3568002(void *data) +{ + if (!of_machine_is_compatible("rockchip,rk3566") && + !of_machine_is_compatible("rockchip,rk3568")) + return false; + + gfp_flags_quirk |= GFP_DMA32; + + return true; +} + static const struct gic_quirk its_quirks[] = { #ifdef CONFIG_CAVIUM_ERRATUM_22375 { @@ -4954,6 +4967,14 @@ static const struct gic_quirk its_quirks[] = { .property = "dma-noncoherent", .init = its_set_non_coherent, }, +#ifdef CONFIG_ROCKCHIP_ERRATUM_3568002 + { + .desc = "ITS: Rockchip erratum RK3568002", + .iidr = 0x0201743b, + .mask = 0xffffffff, + .init = its_enable_rk3568002, + }, +#endif { } }; ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 2/3] arm64: dts: rockchip: rk356x: Add MSI controller node 2025-02-16 22:16 [PATCH v2 0/3] Add Rockchip 3568001/2 errata workarounds and enable ITS on RK356x Dmitry Osipenko 2025-02-16 22:16 ` [PATCH v2 1/3] irqchip/gic-v3: Add Rockchip 3568002 erratum workaround Dmitry Osipenko @ 2025-02-16 22:16 ` Dmitry Osipenko 2025-02-21 9:01 ` [tip: irq/drivers] " tip-bot2 for Dmitry Osipenko 2025-02-16 22:16 ` [PATCH v2 3/3] arm64: dts: rockchip: rk356x: Move PCIe MSI to use GIC ITS instead of MBI Dmitry Osipenko 2 siblings, 1 reply; 7+ messages in thread From: Dmitry Osipenko @ 2025-02-16 22:16 UTC (permalink / raw) To: Heiko Stuebner, Marc Zyngier Cc: Rob Herring, Krzysztof Kozlowski, Thomas Gleixner, devicetree, linux-rockchip, linux-kernel, Kever Yang, XiaoDong Huang, Peter Geis, Robin Murphy, kernel Rockchip 356x SoC's GIC has two hardware integration issues that affect MSI functionality of the GIC. Previously, both these GIC issues were worked around by using MBI for MSI instead of ITS because kernel GIC driver didn't have necessary quirks. First issue is about RK356x GIC not supporting programmable shareability, while reporting it as supported in a GIC's feature register. Rockchip assigned Erratum ID #3568001 for this issue. This patch adds dma-noncoherent property to the GIC node, denoting that a SW workaround is required for mitigating the issue. Second issue is about GIC AXI master interface addressing limited to the first 4GB of physical address space. Rockchip assigned Erratum ID #3568002 for this issue. Now that kernel supports quirks for both of the erratums, add MSI controller node to RK356x device-tree. Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index de5e6c0c3d24..423185686600 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -284,6 +284,18 @@ gic: interrupt-controller@fd400000 { mbi-alias = <0x0 0xfd410000>; mbi-ranges = <296 24>; msi-controller; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dma-noncoherent; + + its: msi-controller@fd440000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfd440000 0 0x20000>; + dma-noncoherent; + msi-controller; + #msi-cells = <1>; + }; }; usb_host0_ehci: usb@fd800000 { -- 2.48.1 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [tip: irq/drivers] arm64: dts: rockchip: rk356x: Add MSI controller node 2025-02-16 22:16 ` [PATCH v2 2/3] arm64: dts: rockchip: rk356x: Add MSI controller node Dmitry Osipenko @ 2025-02-21 9:01 ` tip-bot2 for Dmitry Osipenko 0 siblings, 0 replies; 7+ messages in thread From: tip-bot2 for Dmitry Osipenko @ 2025-02-21 9:01 UTC (permalink / raw) To: linux-tip-commits; +Cc: Dmitry Osipenko, Thomas Gleixner, x86, linux-kernel The following commit has been merged into the irq/drivers branch of tip: Commit-ID: f15be3d4a0a55db2b50f319c378a2d16ceb21f86 Gitweb: https://git.kernel.org/tip/f15be3d4a0a55db2b50f319c378a2d16ceb21f86 Author: Dmitry Osipenko <dmitry.osipenko@collabora.com> AuthorDate: Mon, 17 Feb 2025 01:16:33 +03:00 Committer: Thomas Gleixner <tglx@linutronix.de> CommitterDate: Fri, 21 Feb 2025 09:58:08 +01:00 arm64: dts: rockchip: rk356x: Add MSI controller node Rockchip 356x SoC's GIC has two hardware integration issues that affect MSI functionality of the GIC. Previously, both these GIC issues were worked around by using MBI for MSI instead of ITS because kernel GIC driver didn't have necessary quirks. First issue is about RK356x GIC not supporting programmable shareability, while reporting it as supported in a GIC's feature register. Rockchip assigned Erratum ID #3568001 for this issue. This patch adds dma-noncoherent property to the GIC node, denoting that a SW workaround is required for mitigating the issue. Second issue is about GIC AXI master interface addressing limited to the first 4GB of physical address space. Rockchip assigned Erratum ID #3568002 for this issue. Now that kernel supports quirks for both of the erratums, add MSI controller node to RK356x device-tree. Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20250216221634.364158-3-dmitry.osipenko@collabora.com --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index e553906..89ba0d7 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -284,6 +284,18 @@ mbi-alias = <0x0 0xfd410000>; mbi-ranges = <296 24>; msi-controller; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dma-noncoherent; + + its: msi-controller@fd440000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfd440000 0 0x20000>; + dma-noncoherent; + msi-controller; + #msi-cells = <1>; + }; }; usb_host0_ehci: usb@fd800000 { ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 3/3] arm64: dts: rockchip: rk356x: Move PCIe MSI to use GIC ITS instead of MBI 2025-02-16 22:16 [PATCH v2 0/3] Add Rockchip 3568001/2 errata workarounds and enable ITS on RK356x Dmitry Osipenko 2025-02-16 22:16 ` [PATCH v2 1/3] irqchip/gic-v3: Add Rockchip 3568002 erratum workaround Dmitry Osipenko 2025-02-16 22:16 ` [PATCH v2 2/3] arm64: dts: rockchip: rk356x: Add MSI controller node Dmitry Osipenko @ 2025-02-16 22:16 ` Dmitry Osipenko 2025-02-21 9:01 ` [tip: irq/drivers] " tip-bot2 for Dmitry Osipenko 2 siblings, 1 reply; 7+ messages in thread From: Dmitry Osipenko @ 2025-02-16 22:16 UTC (permalink / raw) To: Heiko Stuebner, Marc Zyngier Cc: Rob Herring, Krzysztof Kozlowski, Thomas Gleixner, devicetree, linux-rockchip, linux-kernel, Kever Yang, XiaoDong Huang, Peter Geis, Robin Murphy, kernel Rockchip 356x device-tree now supports GIC ITS. Move PCIe controller's MSI to use ITS instead of MBI. This removes extra CPU overhead of handling PCIe MBIs by letting GIC's ITS to serve the PCIe MSIs. Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index 423185686600..4f11141ea146 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -969,7 +969,7 @@ pcie2x1: pcie@fe260000 { num-ib-windows = <6>; num-ob-windows = <2>; max-link-speed = <2>; - msi-map = <0x0 &gic 0x0 0x1000>; + msi-map = <0x0 &its 0x0 0x1000>; num-lanes = <1>; phys = <&combphy2 PHY_TYPE_PCIE>; phy-names = "pcie-phy"; -- 2.48.1 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [tip: irq/drivers] arm64: dts: rockchip: rk356x: Move PCIe MSI to use GIC ITS instead of MBI 2025-02-16 22:16 ` [PATCH v2 3/3] arm64: dts: rockchip: rk356x: Move PCIe MSI to use GIC ITS instead of MBI Dmitry Osipenko @ 2025-02-21 9:01 ` tip-bot2 for Dmitry Osipenko 0 siblings, 0 replies; 7+ messages in thread From: tip-bot2 for Dmitry Osipenko @ 2025-02-21 9:01 UTC (permalink / raw) To: linux-tip-commits; +Cc: Dmitry Osipenko, Thomas Gleixner, x86, linux-kernel The following commit has been merged into the irq/drivers branch of tip: Commit-ID: b956c9de91757c9478e24fc9f6a57fd46f0a49f0 Gitweb: https://git.kernel.org/tip/b956c9de91757c9478e24fc9f6a57fd46f0a49f0 Author: Dmitry Osipenko <dmitry.osipenko@collabora.com> AuthorDate: Mon, 17 Feb 2025 01:16:34 +03:00 Committer: Thomas Gleixner <tglx@linutronix.de> CommitterDate: Fri, 21 Feb 2025 09:58:08 +01:00 arm64: dts: rockchip: rk356x: Move PCIe MSI to use GIC ITS instead of MBI Rockchip 356x device-tree now supports GIC ITS. Move PCIe controller's MSI to use ITS instead of MBI. This removes extra CPU overhead of handling PCIe MBIs by letting GIC's ITS to serve the PCIe MSIs. Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20250216221634.364158-4-dmitry.osipenko@collabora.com --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index 89ba0d7..4e730ae 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -969,7 +969,7 @@ num-ib-windows = <6>; num-ob-windows = <2>; max-link-speed = <2>; - msi-map = <0x0 &gic 0x0 0x1000>; + msi-map = <0x0 &its 0x0 0x1000>; num-lanes = <1>; phys = <&combphy2 PHY_TYPE_PCIE>; phy-names = "pcie-phy"; ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2025-02-21 9:01 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2025-02-16 22:16 [PATCH v2 0/3] Add Rockchip 3568001/2 errata workarounds and enable ITS on RK356x Dmitry Osipenko 2025-02-16 22:16 ` [PATCH v2 1/3] irqchip/gic-v3: Add Rockchip 3568002 erratum workaround Dmitry Osipenko 2025-02-21 9:01 ` [tip: irq/drivers] " tip-bot2 for Dmitry Osipenko 2025-02-16 22:16 ` [PATCH v2 2/3] arm64: dts: rockchip: rk356x: Add MSI controller node Dmitry Osipenko 2025-02-21 9:01 ` [tip: irq/drivers] " tip-bot2 for Dmitry Osipenko 2025-02-16 22:16 ` [PATCH v2 3/3] arm64: dts: rockchip: rk356x: Move PCIe MSI to use GIC ITS instead of MBI Dmitry Osipenko 2025-02-21 9:01 ` [tip: irq/drivers] " tip-bot2 for Dmitry Osipenko
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