[PATCH v3 0/2] (no cover subject)

[PATCH v3 0/2] (no cover subject)

[Zixian Zeng]

This is tested on milkv-pioneer board. Using driver/spi/spidev.c
for creating /dev/spidevX.Y and tools/spi/spidev_test for testing
functionality.

Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
---
Changes in v3:
- disable the spi status on sg2042-milkv-pioneer board
- create dt-binding of compatible property
- replace the general compatible property with SoC-specific in dts
- Link to v2: https://lore.kernel.org/r/20250228-sfg-spi-v2-1-8bbf23b85d0e@gmail.com

Changes in v2:
- rebase v1 to sophgo/master(github.com/sophgo/linux.git).
- order properties in device node.
- remove unevaluated properties `clock-frequency`.
- set default status to disable.
- Link to v1: https://lore.kernel.org/r/20250228-sfg-spi-v1-1-b989aed94911@gmail.com

---
Zixian Zeng (2):
      spi: dt-bindings: snps,dw-apb-ssi: Add compatible for SOPHGO SG2042 SoC
      riscv: sophgo: dts: Add spi controller for SG2042

 .../devicetree/bindings/spi/snps,dw-apb-ssi.yaml   |  4 ++++
 arch/riscv/boot/dts/sophgo/sg2042.dtsi             | 26 ++++++++++++++++++++++
 2 files changed, 30 insertions(+)
---
base-commit: aa5ee7180ec41bb77c3e327e95d119f2294babea
change-id: 20250228-sfg-spi-e3f2aeca09ab

Best regards,
-- 
Zixian Zeng <sycamoremoon376@gmail.com>

[PATCH v3 1/2] spi: dt-bindings: snps,dw-apb-ssi: Add compatible for SOPHGO SG2042 SoC

[Zixian Zeng]

add compatible property to include "sophgo,sg2042-spi" for
the SOPHGO SG2042 SoC SPI Controller.

Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
---
 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
index bccd00a1ddd0ad92b437eed5b525a6ea1963db57..33fb21267df2594e68419cfb980a40909868e337 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
@@ -92,6 +92,10 @@ properties:
         items:
           - const: thead,th1520-spi
           - const: snps,dw-apb-ssi
+      - description: SOPHGO SG2042 SoC SPI Controller
+        items:
+          - const: sophgo,sg2042-spi
+          - const: snps,dw-apb-ssi
 
   reg:
     minItems: 1

-- 
2.48.1

Re: [PATCH v3 1/2] spi: dt-bindings: snps,dw-apb-ssi: Add compatible for SOPHGO SG2042 SoC

[Krzysztof Kozlowski]

On 13/03/2025 14:11, Zixian Zeng wrote:
> add compatible property to include "sophgo,sg2042-spi" for
> the SOPHGO SG2042 SoC SPI Controller.
> 
> Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
> ---
>  Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> index bccd00a1ddd0ad92b437eed5b525a6ea1963db57..33fb21267df2594e68419cfb980a40909868e337 100644
> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> @@ -92,6 +92,10 @@ properties:
>          items:
>            - const: thead,th1520-spi
>            - const: snps,dw-apb-ssi
> +      - description: SOPHGO SG2042 SoC SPI Controller

Please do not add things to the end - it increases conflicts and makes
it difficult to find entries when reading the code. Place it after Renesas.


Best regards,
Krzysztof

[PATCH v3 2/2] riscv: sophgo: dts: Add spi controller for SG2042

[Zixian Zeng]

Add spi controllers for SG2042.

SG2042 uses the upstreamed Synopsys DW SPI IP.

Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
---
 arch/riscv/boot/dts/sophgo/sg2042.dtsi | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index e62ac51ac55abd922b5ef796ba8c2196383850c4..9e0ec64e91a2330698aea202c8f0a2ca1f7e0919 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -545,5 +545,31 @@ sd: mmc@704002b000 {
 				      "timer";
 			status = "disabled";
 		};
+
+		spi0: spi@7040004000 {
+			compatible = "sophgo,sg2042-spi", "snps,dw-apb-ssi";
+			reg = <0x70 0x40004000 0x00 0x1000>;
+			clocks = <&clkgen GATE_CLK_APB_SPI>;
+			interrupt-parent = <&intc>;
+			interrupts = <110 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			num-cs = <2>;
+			resets = <&rstgen RST_SPI0>;
+			status = "disabled";
+		};
+
+		spi1: spi@7040005000 {
+			compatible = "sophgo,sg2042-spi", "snps,dw-apb-ssi";
+			reg = <0x70 0x40005000 0x00 0x1000>;
+			clocks = <&clkgen GATE_CLK_APB_SPI>;
+			interrupt-parent = <&intc>;
+			interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			num-cs = <2>;
+			resets = <&rstgen RST_SPI1>;
+			status = "disabled";
+		};
 	};
 };

-- 
2.48.1

Re: [PATCH v3 2/2] riscv: sophgo: dts: Add spi controller for SG2042

[Krzysztof Kozlowski]

On 13/03/2025 14:11, Zixian Zeng wrote:
> Add spi controllers for SG2042.
> 
> SG2042 uses the upstreamed Synopsys DW SPI IP.
> 
> Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
> ---
>  arch/riscv/boot/dts/sophgo/sg2042.dtsi | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> index e62ac51ac55abd922b5ef796ba8c2196383850c4..9e0ec64e91a2330698aea202c8f0a2ca1f7e0919 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> @@ -545,5 +545,31 @@ sd: mmc@704002b000 {
>  				      "timer";
>  			status = "disabled";
>  		};
> +
> +		spi0: spi@7040004000 {

Does not look like you keep order by unit address (see DTS coding style).


Best regards,
Krzysztof

Re: [PATCH v3 2/2] riscv: sophgo: dts: Add spi controller for SG2042

[Zixian Zeng]

On 25/03/13 02:43PM, Krzysztof Kozlowski wrote:
> On 13/03/2025 14:11, Zixian Zeng wrote:
> > Add spi controllers for SG2042.
> > 
> > SG2042 uses the upstreamed Synopsys DW SPI IP.
> > 
> > Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
> > ---
> >  arch/riscv/boot/dts/sophgo/sg2042.dtsi | 26 ++++++++++++++++++++++++++
> >  1 file changed, 26 insertions(+)
> > 
> > diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> > index e62ac51ac55abd922b5ef796ba8c2196383850c4..9e0ec64e91a2330698aea202c8f0a2ca1f7e0919 100644
> > --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> > +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> > @@ -545,5 +545,31 @@ sd: mmc@704002b000 {
> >  				      "timer";
> >  			status = "disabled";
> >  		};
> > +
> > +		spi0: spi@7040004000 {
> 
> Does not look like you keep order by unit address (see DTS coding style).
> 
Thanks for reminding, I will read it more carefully.
> 
> Best regards,
> Krzysztof

Best regards,
Zixian Zeng

Re: [PATCH v3 0/2] (no cover subject)

[Chen Wang]

Hi, Zixian,

First, it looks like you forgot to write a subject line for your email.

On 2025/3/13 21:11, Zixian Zeng wrote:
> This is tested on milkv-pioneer board. Using driver/spi/spidev.c
> for creating /dev/spidevX.Y and tools/spi/spidev_test for testing
> functionality.
Second, why is there no description of what was changed in the patch 
set? Maybe it was missed.

Introduction to testing can be used as supplementary information, but it 
should not be the main body of this email.

> Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
> ---
> Changes in v3:
> - disable the spi status on sg2042-milkv-pioneer board
Not "disable", should be "Remove", and please capitalize the first 
letter of the sentences.
> - create dt-binding of compatible property
> - replace the general compatible property with SoC-specific in dts
Another relatively important change is about the clock, which you seem 
to have missed.
> - Link to v2: https://lore.kernel.org/r/20250228-sfg-spi-v2-1-8bbf23b85d0e@gmail.com
>
> Changes in v2:
> - rebase v1 to sophgo/master(github.com/sophgo/linux.git).
> - order properties in device node.
> - remove unevaluated properties `clock-frequency`.
> - set default status to disable.
> - Link to v1: https://lore.kernel.org/r/20250228-sfg-spi-v1-1-b989aed94911@gmail.com
>
> ---
> Zixian Zeng (2):
>        spi: dt-bindings: snps,dw-apb-ssi: Add compatible for SOPHGO SG2042 SoC
>        riscv: sophgo: dts: Add spi controller for SG2042
>
>   .../devicetree/bindings/spi/snps,dw-apb-ssi.yaml   |  4 ++++
>   arch/riscv/boot/dts/sophgo/sg2042.dtsi             | 26 ++++++++++++++++++++++
>   2 files changed, 30 insertions(+)
> ---
> base-commit: aa5ee7180ec41bb77c3e327e95d119f2294babea
> change-id: 20250228-sfg-spi-e3f2aeca09ab
>
> Best regards,

BTW, I suggest you wait until 6.15-rc1 comes out before submitting the 
next version, because I have already sent a PR to Arnd for Sophgo DTS.

Regards,

Chen

Re: [PATCH v3 0/2] (no cover subject)

[Zixian Zeng]

On 25/03/14 08:11AM, Chen Wang wrote:
> Hi, Zixian,
> 
> First, it looks like you forgot to write a subject line for your email.
> 
> On 2025/3/13 21:11, Zixian Zeng wrote:
> > This is tested on milkv-pioneer board. Using driver/spi/spidev.c
> > for creating /dev/spidevX.Y and tools/spi/spidev_test for testing
> > functionality.
> Second, why is there no description of what was changed in the patch set?
> Maybe it was missed.
> 
I was intended to avoid duplication with commit msg, but it seems unnecessary.
I will try to write a better cover letter next time. Thanks for your review.
> Introduction to testing can be used as supplementary information, but it
> should not be the main body of this email.
> 
> > Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
> > ---
> > Changes in v3:
> > - disable the spi status on sg2042-milkv-pioneer board
> Not "disable", should be "Remove", and please capitalize the first letter of
> the sentences.
> > - create dt-binding of compatible property
> > - replace the general compatible property with SoC-specific in dts
> Another relatively important change is about the clock, which you seem to
> have missed.
My mistake, I will add it in the next version.
> > - Link to v2: https://lore.kernel.org/r/20250228-sfg-spi-v2-1-8bbf23b85d0e@gmail.com
> > 
> > Changes in v2:
> > - rebase v1 to sophgo/master(github.com/sophgo/linux.git).
> > - order properties in device node.
> > - remove unevaluated properties `clock-frequency`.
> > - set default status to disable.
> > - Link to v1: https://lore.kernel.org/r/20250228-sfg-spi-v1-1-b989aed94911@gmail.com
> > 
> > ---
> > Zixian Zeng (2):
> >        spi: dt-bindings: snps,dw-apb-ssi: Add compatible for SOPHGO SG2042 SoC
> >        riscv: sophgo: dts: Add spi controller for SG2042
> > 
> >   .../devicetree/bindings/spi/snps,dw-apb-ssi.yaml   |  4 ++++
> >   arch/riscv/boot/dts/sophgo/sg2042.dtsi             | 26 ++++++++++++++++++++++
> >   2 files changed, 30 insertions(+)
> > ---
> > base-commit: aa5ee7180ec41bb77c3e327e95d119f2294babea
> > change-id: 20250228-sfg-spi-e3f2aeca09ab
> > 
> > Best regards,
> 
> BTW, I suggest you wait until 6.15-rc1 comes out before submitting the next
> version, because I have already sent a PR to Arnd for Sophgo DTS.
> 
Sure, I will keep an eye on the release.
> Regards,
> 
> Chen
> 
Best regards,
Zixian Zeng

[PATCH v3 0/2] (no cover subject)

[Priyank Rathod]

Changes in v3:
- Updated cover letter and auto-populated maintainer To/Cc trailers.
- Updated commit formatting per checkpatch guidelines.
- Link to v2: https://lore.kernel.org/r/20260803-b4-fix-aer-memleaks-v2-0-d2be03d9864b@google.com

PCI/AER: Fix ghes_estatus_pool memory leaks in error handling

This series addresses two memory leaks in PCIe Advanced Error Reporting (AER)
handling where memory snapshot buffers allocated from ghes_estatus_pool
are not released back to the pool.

When firmware reports PCIe errors via ACPI APEI GHES (ghes_handle_aer()), it
allocates a buffer from ghes_estatus_pool for aer_capability_regs and
enqueues it into aer_recover_ring. If errors are dropped or skipped, these
buffers must be freed to prevent ghes_estatus_pool memory exhaustion.

Patch 1: Fixes memory leak in aer_recover_queue() when kfifo_in_spinlocked()
         fails due to a buffer overflow (ring capacity of 16 entries full).
Patch 2: Fixes memory leak in aer_recover_work_func() when a dequeued entry
         cannot be mapped to a PCI device (pdev is NULL).

Changes in v2:
  - Refactored aer_recover_work_func() to ensure ghes_estatus_pool_region_free()
    is called unconditionally for every dequeued record.
  - Added Patch 2 to fix related memory leak in aer_recover_queue() on
    kfifo buffer overflow.
  - Updated commit messages with detailed pool lifetime explanations.

Priyank Rathod (2):
  PCI/AER: Fix memory leak in aer_recover_queue() on kfifo buffer overflow
  PCI/AER: Fix memory leak in aer_recover_work_func() when pci_dev is missing

 drivers/pci/pcie/aer.c | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

Signed-off-by: Priyank Rathod <rathodpriyank@google.com>
---
Changes in v3:
- Updated cover letter and auto-populated maintainer To/Cc trailers.
- Updated commit formatting per checkpatch guidelines.
- Link to v2: https://lore.kernel.org/r/20260803-b4-fix-aer-memleaks-v2-0-d2be03d9864b@google.com

Changes in v2:
- Refactored aer_recover_work_func() to ensure ghes_estatus_pool_region_free()
  is called unconditionally for every dequeued record.
- Added Patch 2 to fix related memory leak in aer_recover_queue() on
  kfifo buffer overflow.
- Link to v1: https://lore.kernel.org/r/20260803183853.432459-2-rathodpriyank@google.com

---
Priyank Rathod (2):
      PCI/AER: Fix memory leak in aer_recover_queue() on kfifo buffer overflow
      PCI/AER: Fix memory leak in aer_recover_work_func() when pci_dev is missing

 drivers/pci/pcie/aer.c | 28 ++++++++++++++++------------
 1 file changed, 16 insertions(+), 12 deletions(-)
---
base-commit: 248951ddc14de84de3910f9b13f51491a8cd91df
change-id: 20260803-b4-fix-aer-memleaks-524a1bd5e888

Best regards,
-- 
Priyank Rathod <rathodpriyank@google.com>

[PATCH v3 0/2] (no cover subject)

[Linus Walleij]

This type of firmware partition appear in some devices in
NAND flash, so we need to be able to tag the partitions
with the appropriate type.

The origin of the "SEAttle iMAge" is unknown.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
Changes in v3:
- Drop reference from partitions.yaml again
- Drop select: false
- Use unevaluatedProperties
- Link to v2: https://lore.kernel.org/r/20230705-seama-partitions-v2-0-9d349f0d5ab7@linaro.org

Changes in v2:
- Make the binding clearly childless
- Link to v1: https://lore.kernel.org/r/20230506-seama-partitions-v1-0-5806af1e4ac7@linaro.org

---
Linus Walleij (2):
      dt-bindings: mtd: Add SEAMA partition bindings
      ARM: dts: bcm5301x: Add SEAMA compatibles

 .../devicetree/bindings/mtd/partitions/seama.yaml  | 48 ++++++++++++++++++++++
 arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts      |  1 +
 arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts      |  1 +
 3 files changed, 50 insertions(+)
---
base-commit: 035cd1416934ef7ae5374272d3c9e378c3d7049c
change-id: 20230506-seama-partitions-b620117b9985

Best regards,
-- 
Linus Walleij <linus.walleij@linaro.org>