From: Ben Zong-You Xie <ben717@andestech.com>
To: <devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Cc: <paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
<aou@eecs.berkeley.edu>, <alex@ghiti.fr>, <robh@kernel.org>,
<krzk+dt@kernel.org>, <conor+dt@kernel.org>, <tglx@linutronix.de>,
<daniel.lezcano@linaro.org>,
<prabhakar.mahadev-lad.rj@bp.renesas.com>, <tim609@andestech.com>,
"Ben Zong-You Xie" <ben717@andestech.com>
Subject: [PATCH 0/9] add Voyager board support
Date: Mon, 7 Apr 2025 18:49:28 +0800 [thread overview]
Message-ID: <20250407104937.315783-1-ben717@andestech.com> (raw)
The Voyager is a 9.6” x 9.6” Micro ATX form factor development board including
Andes QiLai SoC. This patch series adds minimal device tree files for the QiLai
SoC and the Voyager board [1].
Now only support basic uart drivers to boot up into a basic console. Other
features will be added later.
[1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
Ben Zong-You Xie (9):
riscv: add Andes SoC family Kconfig support
dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings
dt-bindings: interrupt-controller: add Andes QiLai PLIC
dt-bindings: interrupt-controller: add Andes machine-level software
interrupt controller
dt-bindings: timer: add Andes machine timer
dt-bindings: cache: ax45mp-cache: allow variable cache-sets for Andes
L2 cache
riscv: dts: andes: add QiLai SoC device tree
riscv: dts: andes: add Voyager board device tree
riscv: defconfig: enable Andes SoC
.../cache/andestech,ax45mp-cache.yaml | 2 +-
.../andestech,plicsw.yaml | 48 +++++
.../sifive,plic-1.0.0.yaml | 1 +
.../devicetree/bindings/riscv/andes.yaml | 25 +++
.../bindings/timer/andestech,plmt0.yaml | 42 ++++
MAINTAINERS | 8 +
arch/riscv/Kconfig.errata | 2 +-
arch/riscv/Kconfig.socs | 9 +
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/andes/Makefile | 2 +
arch/riscv/boot/dts/andes/qilai-voyager.dts | 19 ++
arch/riscv/boot/dts/andes/qilai.dtsi | 194 ++++++++++++++++++
arch/riscv/configs/defconfig | 1 +
13 files changed, 352 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
create mode 100644 Documentation/devicetree/bindings/riscv/andes.yaml
create mode 100644 Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
create mode 100644 arch/riscv/boot/dts/andes/Makefile
create mode 100644 arch/riscv/boot/dts/andes/qilai-voyager.dts
create mode 100644 arch/riscv/boot/dts/andes/qilai.dtsi
--
2.34.1
next reply other threads:[~2025-04-07 11:13 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-07 10:49 Ben Zong-You Xie [this message]
2025-04-07 10:49 ` [PATCH 1/9] riscv: add Andes SoC family Kconfig support Ben Zong-You Xie
2025-04-07 10:49 ` [PATCH 2/9] dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings Ben Zong-You Xie
2025-04-07 14:13 ` Rob Herring (Arm)
2025-04-07 10:49 ` [PATCH 3/9] dt-bindings: interrupt-controller: add Andes QiLai PLIC Ben Zong-You Xie
2025-04-07 14:14 ` Rob Herring (Arm)
2025-04-07 10:49 ` [PATCH 4/9] dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller Ben Zong-You Xie
2025-04-07 14:17 ` Rob Herring
2025-04-21 12:19 ` Ben Zong-You Xie
2025-04-07 10:49 ` [PATCH 5/9] dt-bindings: timer: add Andes machine timer Ben Zong-You Xie
2025-04-07 14:18 ` Rob Herring
2025-04-07 10:49 ` [PATCH 6/9] dt-bindings: cache: ax45mp-cache: allow variable cache-sets for Andes L2 cache Ben Zong-You Xie
2025-04-07 14:19 ` Rob Herring (Arm)
2025-04-07 10:49 ` [PATCH 7/9] riscv: dts: andes: add QiLai SoC device tree Ben Zong-You Xie
2025-04-07 14:30 ` Krzysztof Kozlowski
2025-04-08 16:43 ` Conor Dooley
2025-04-07 10:49 ` [PATCH 8/9] riscv: dts: andes: add Voyager board " Ben Zong-You Xie
2025-04-07 14:31 ` Krzysztof Kozlowski
2025-04-07 10:49 ` [PATCH 9/9] riscv: defconfig: enable Andes SoC Ben Zong-You Xie
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