From: Peter Zijlstra <peterz@infradead.org>
To: "Clément Léger" <cleger@rivosinc.com>
Cc: Alexandre Ghiti <alex@ghiti.fr>,
"open list:DOCUMENTATION" <linux-doc@vger.kernel.org>,
open list <linux-kernel@vger.kernel.org>,
"open list:RISC-V ARCHITECTURE" <linux-riscv@lists.infradead.org>,
"open list:KERNEL SELFTEST FRAMEWORK"
<linux-kselftest@vger.kernel.org>,
Jonathan Corbet <corbet@lwn.net>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>, Shuah Khan <shuah@kernel.org>,
Andrew Jones <ajones@ventanamicro.com>,
Samuel Holland <samuel.holland@sifive.com>
Subject: Re: [PATCH 1/5] riscv: misaligned: factorize trap handling
Date: Tue, 22 Apr 2025 11:44:19 +0200 [thread overview]
Message-ID: <20250422094419.GC14170@noisy.programming.kicks-ass.net> (raw)
In-Reply-To: <2c4f4422-d9c9-4d36-b0ef-f68779b91ee9@rivosinc.com>
On Tue, Apr 22, 2025 at 09:57:12AM +0200, Clément Léger wrote:
>
>
> On 21/04/2025 09:06, Alexandre Ghiti wrote:
> > Hi Clément,
> >
> >
> > On 14/04/2025 14:34, Clément Léger wrote:
> >> misaligned accesses traps are not nmi and should be treated as normal
> >> one using irqentry_enter()/exit().
> >
> >
> > All the traps that come from kernel mode are treated as nmi as it was
> > suggested by Peter here: https://lore.kernel.org/linux-riscv/
> > Yyhv4UUXuSfvMOw+@hirez.programming.kicks-ass.net/
> >
> > I don't know the differences between irq_nmi_entry/exit() and irq_entry/
> > exit(), so is that still correct to now treat the kernel traps as non-nmi?
>
> Hi Alex,
>
> Actually, this discussion was raised on a previous series [1] by Maciej
> which replied that we should actually reenable interrupt depending on
> the state that was interrupted. Looking at other architecture/code, it
> seems like treating misaligned accesses as NMI is probably not the right
> way. For instance, loongarch treats them as normal IRQ using a
> irqentry_enter()/exit() and reenabling IRQS if possible.
So, a trap that happens in kernel space while IRQs are disabled, SHOULD
really be NMI-like.
You then have a choice, make all such traps from kernel space NMI-like;
this makes it easy on the trap handler, since the context is always the
same. Mistakes are 'easy' to find.
Or,.. do funny stuff and only make it NMI like if IRQs were disabled.
Which gives inconsistent context for the handler and you'll find
yourself scratching your head at some point in the future wondering why
this one rare occasion goes BOOM.
x86 mostly does the first, any trap that can happen with IRQs disabled
is treated unconditionally as NMI like. The obvious exception is
page-fault, but that already has a from-non-preemptible-context branch
that is 'careful'.
As to unaligned traps from kernel space, I would imagine they mostly BUG
the kernel, except when there's an exception entry for that location, in
which case it might do a fixup?
Anyway, the reason these exceptions should be NMI like, is because
interrupts are not allowed to nest. Notably something like:
raw_spin_lock_irqsave(&foo);
<IRQ>
raw_spin_lock_irqsave(&foo);
...
Is an obvious problem. Exceptions that can run while IRQs are disabled,
must not use locks -- treating them as NMI-like (they are non-maskable
after all), ensures this.
next prev parent reply other threads:[~2025-04-22 9:44 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-14 12:34 [PATCH 0/5] riscv: misaligned: fix interruptible context and add tests Clément Léger
2025-04-14 12:34 ` [PATCH 1/5] riscv: misaligned: factorize trap handling Clément Léger
2025-04-21 7:06 ` Alexandre Ghiti
2025-04-22 7:57 ` Clément Léger
2025-04-22 9:44 ` Peter Zijlstra [this message]
2025-04-22 10:17 ` Clément Léger
2025-05-01 20:41 ` Maciej W. Rozycki
2025-05-01 20:51 ` Maciej W. Rozycki
2025-04-14 12:34 ` [PATCH 2/5] riscv: misaligned: enable IRQs while handling misaligned accesses Clément Léger
2025-04-21 7:13 ` Alexandre Ghiti
2025-04-14 12:34 ` [PATCH 3/5] riscv: misaligned: use get_user() instead of __get_user() Clément Léger
2025-04-21 7:21 ` Alexandre Ghiti
2025-04-14 12:34 ` [PATCH 4/5] Documentation/sysctl: add riscv to unaligned-trap supported archs Clément Léger
2025-04-21 7:22 ` Alexandre Ghiti
2025-04-14 12:34 ` [PATCH 5/5] selftests: riscv: add misaligned access testing Clément Léger
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