From: Alexandre Ghiti <alex@ghiti.fr>
To: "Clément Léger" <cleger@rivosinc.com>,
"open list:DOCUMENTATION" <linux-doc@vger.kernel.org>,
"open list" <linux-kernel@vger.kernel.org>,
"open list:RISC-V ARCHITECTURE" <linux-riscv@lists.infradead.org>,
"open list:KERNEL SELFTEST FRAMEWORK"
<linux-kselftest@vger.kernel.org>
Cc: Jonathan Corbet <corbet@lwn.net>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>, Shuah Khan <shuah@kernel.org>,
Andrew Jones <ajones@ventanamicro.com>,
Samuel Holland <samuel.holland@sifive.com>
Subject: Re: [PATCH 3/5] riscv: misaligned: use get_user() instead of __get_user()
Date: Mon, 21 Apr 2025 09:21:20 +0200 [thread overview]
Message-ID: <cd642ab7-e6ea-459b-89f7-63b12505f576@ghiti.fr> (raw)
In-Reply-To: <20250414123543.1615478-4-cleger@rivosinc.com>
On 14/04/2025 14:34, Clément Léger wrote:
> Now that we can safely handle user memory accesses while in the
> misaligned access handlers, use get_user() instead of __get_user() to
> have user memory access checks.
>
> Signed-off-by: Clément Léger <cleger@rivosinc.com>
> ---
> arch/riscv/kernel/traps_misaligned.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
> index 4354c87c0376..97c674d7d34f 100644
> --- a/arch/riscv/kernel/traps_misaligned.c
> +++ b/arch/riscv/kernel/traps_misaligned.c
> @@ -268,7 +268,7 @@ static unsigned long get_f32_rs(unsigned long insn, u8 fp_reg_offset,
> int __ret; \
> \
> if (user_mode(regs)) { \
> - __ret = __get_user(insn, (type __user *) insn_addr); \
> + __ret = get_user(insn, (type __user *) insn_addr); \
> } else { \
> insn = *(type *)insn_addr; \
> __ret = 0; \
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Thanks,
Alex
next prev parent reply other threads:[~2025-04-21 7:21 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-14 12:34 [PATCH 0/5] riscv: misaligned: fix interruptible context and add tests Clément Léger
2025-04-14 12:34 ` [PATCH 1/5] riscv: misaligned: factorize trap handling Clément Léger
2025-04-21 7:06 ` Alexandre Ghiti
2025-04-22 7:57 ` Clément Léger
2025-04-22 9:44 ` Peter Zijlstra
2025-04-22 10:17 ` Clément Léger
2025-05-01 20:41 ` Maciej W. Rozycki
2025-05-01 20:51 ` Maciej W. Rozycki
2025-04-14 12:34 ` [PATCH 2/5] riscv: misaligned: enable IRQs while handling misaligned accesses Clément Léger
2025-04-21 7:13 ` Alexandre Ghiti
2025-04-14 12:34 ` [PATCH 3/5] riscv: misaligned: use get_user() instead of __get_user() Clément Léger
2025-04-21 7:21 ` Alexandre Ghiti [this message]
2025-04-14 12:34 ` [PATCH 4/5] Documentation/sysctl: add riscv to unaligned-trap supported archs Clément Léger
2025-04-21 7:22 ` Alexandre Ghiti
2025-04-14 12:34 ` [PATCH 5/5] selftests: riscv: add misaligned access testing Clément Léger
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