From: Inochi Amaoto <inochiama@gmail.com>
To: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Chen Wang <unicorn_wang@outlook.com>,
Inochi Amaoto <inochiama@gmail.com>,
Alexander Sverdlin <alexander.sverdlin@gmail.com>,
Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
sophgo@lists.linux.dev, linux-kernel@vger.kernel.org,
Yixun Lan <dlan@gentoo.org>, Longbin Li <looong.bin@gmail.com>
Subject: [PATCH 1/4] riscv: dts: sophgo: Move all soc specific device into soc dtsi file
Date: Wed, 30 Apr 2025 09:26:50 +0800 [thread overview]
Message-ID: <20250430012654.235830-2-inochiama@gmail.com> (raw)
In-Reply-To: <20250430012654.235830-1-inochiama@gmail.com>
Although the cv1800b/cv1812h/sg2000/sg2002 share most peripherals,
some basic peripherals, like clock, pinctrl, clint and plint, are
not shared. These are caused by not only historical reason (plic,
clint), but also the fact the device is not the same (clock, pinctrl).
It is good to override device compatible when the soc number is small,
but now it is a burden for maintenance, and it is kind of annoyed to
explain why using override. So it is time to move this out of the
common peripheral header.
Move all soc related peripherla device from common peripheral header
to the soc specific header to get rid of most compatible override.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 38 +++++++++++++++++--------
arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 38 +++++++++++++++++--------
arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 22 --------------
arch/riscv/boot/dts/sophgo/sg2002.dtsi | 38 +++++++++++++++++--------
4 files changed, 78 insertions(+), 58 deletions(-)
diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
index aa1f5df100f0..fc9e6b56790f 100644
--- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
@@ -15,23 +15,37 @@ memory@80000000 {
};
soc {
+ interrupt-parent = <&plic>;
+ dma-noncoherent;
+
pinctrl: pinctrl@3001000 {
compatible = "sophgo,cv1800b-pinctrl";
reg = <0x03001000 0x1000>,
<0x05027000 0x1000>;
reg-names = "sys", "rtc";
};
+
+ clk: clock-controller@3002000 {
+ compatible = "sophgo,cv1800-clk";
+ reg = <0x03002000 0x1000>;
+ clocks = <&osc>;
+ #clock-cells = <1>;
+ };
+
+ plic: interrupt-controller@70000000 {
+ compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
+ reg = <0x70000000 0x4000000>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ riscv,ndev = <101>;
+ };
+
+ clint: timer@74000000 {
+ compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
+ reg = <0x74000000 0x10000>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
+ };
};
};
-
-&plic {
- compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
-};
-
-&clint {
- compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
-};
-
-&clk {
- compatible = "sophgo,cv1800-clk";
-};
diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
index 8a1b95c5116b..fcea4376fb79 100644
--- a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
@@ -17,23 +17,37 @@ memory@80000000 {
};
soc {
+ interrupt-parent = <&plic>;
+ dma-noncoherent;
+
pinctrl: pinctrl@3001000 {
compatible = "sophgo,cv1812h-pinctrl";
reg = <0x03001000 0x1000>,
<0x05027000 0x1000>;
reg-names = "sys", "rtc";
};
+
+ clk: clock-controller@3002000 {
+ compatible = "sophgo,cv1810-clk";
+ reg = <0x03002000 0x1000>;
+ clocks = <&osc>;
+ #clock-cells = <1>;
+ };
+
+ plic: interrupt-controller@70000000 {
+ compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
+ reg = <0x70000000 0x4000000>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ riscv,ndev = <101>;
+ };
+
+ clint: timer@74000000 {
+ compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
+ reg = <0x74000000 0x10000>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
+ };
};
};
-
-&plic {
- compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
-};
-
-&clint {
- compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
-};
-
-&clk {
- compatible = "sophgo,cv1810-clk";
-};
diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
index c18822ec849f..805b694aa814 100644
--- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
@@ -49,18 +49,10 @@ osc: oscillator {
soc {
compatible = "simple-bus";
- interrupt-parent = <&plic>;
#address-cells = <1>;
#size-cells = <1>;
- dma-noncoherent;
ranges;
- clk: clock-controller@3002000 {
- reg = <0x03002000 0x1000>;
- clocks = <&osc>;
- #clock-cells = <1>;
- };
-
gpio0: gpio@3020000 {
compatible = "snps,dw-apb-gpio";
reg = <0x3020000 0x1000>;
@@ -344,19 +336,5 @@ dmac: dma-controller@4330000 {
snps,data-width = <4>;
status = "disabled";
};
-
- plic: interrupt-controller@70000000 {
- reg = <0x70000000 0x4000000>;
- interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <2>;
- riscv,ndev = <101>;
- };
-
- clint: timer@74000000 {
- reg = <0x74000000 0x10000>;
- interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
- };
};
};
diff --git a/arch/riscv/boot/dts/sophgo/sg2002.dtsi b/arch/riscv/boot/dts/sophgo/sg2002.dtsi
index 7f79de33163c..df133831bd3e 100644
--- a/arch/riscv/boot/dts/sophgo/sg2002.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2002.dtsi
@@ -17,27 +17,41 @@ memory@80000000 {
};
soc {
+ interrupt-parent = <&plic>;
+ dma-noncoherent;
+
pinctrl: pinctrl@3001000 {
compatible = "sophgo,sg2002-pinctrl";
reg = <0x03001000 0x1000>,
<0x05027000 0x1000>;
reg-names = "sys", "rtc";
};
+
+ clk: clock-controller@3002000 {
+ compatible = "sophgo,sg2000-clk";
+ reg = <0x03002000 0x1000>;
+ clocks = <&osc>;
+ #clock-cells = <1>;
+ };
+
+ plic: interrupt-controller@70000000 {
+ compatible = "sophgo,sg2002-plic", "thead,c900-plic";
+ reg = <0x70000000 0x4000000>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ riscv,ndev = <101>;
+ };
+
+ clint: timer@74000000 {
+ compatible = "sophgo,sg2002-clint", "thead,c900-clint";
+ reg = <0x74000000 0x10000>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
+ };
};
};
-&plic {
- compatible = "sophgo,sg2002-plic", "thead,c900-plic";
-};
-
-&clint {
- compatible = "sophgo,sg2002-clint", "thead,c900-clint";
-};
-
-&clk {
- compatible = "sophgo,sg2000-clk";
-};
-
&sdhci0 {
compatible = "sophgo,sg2002-dwcmshc";
};
--
2.49.0
next prev parent reply other threads:[~2025-04-30 1:27 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-30 1:26 [PATCH 0/4] riscv: sophgo: cv18xx: dts rework, part 1 Inochi Amaoto
2025-04-30 1:26 ` Inochi Amaoto [this message]
2025-04-30 15:19 ` [PATCH 1/4] riscv: dts: sophgo: Move all soc specific device into soc dtsi file Alexander Sverdlin
2025-05-02 0:43 ` Yixun Lan
2025-04-30 1:26 ` [PATCH 2/4] riscv: dts: sophgo: Move riscv cpu definition to a separate file Inochi Amaoto
2025-04-30 1:26 ` [PATCH 3/4] riscv: dts: sophgo: rename header file cv18xx.dtsi to cv180x.dtsi Inochi Amaoto
2025-04-30 15:25 ` Alexander Sverdlin
2025-04-30 1:26 ` [PATCH 4/4] riscv: dts: sopgho: use SOC_PERIPHERAL_IRQ to calculate interrupt number Inochi Amaoto
2025-05-13 4:18 ` [PATCH 0/4] riscv: sophgo: cv18xx: dts rework, part 1 Inochi Amaoto
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