From: Konrad Dybcio <konradybcio@kernel.org>
To: Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Clark <robdclark@gmail.com>,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
Dmitry Baryshkov <lumag@kernel.org>,
Akhil P Oommen <quic_akhilpo@quicinc.com>,
Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>,
Simona Vetter <simona@ffwll.ch>
Cc: Marijn Suijten <marijn.suijten@somainline.org>,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Subject: [PATCH RFT v2 14/15] soc: qcom: ubwc: Add #defines for UBWC swizzle bits
Date: Wed, 14 May 2025 17:10:34 +0200 [thread overview]
Message-ID: <20250514-topic-ubwc_central-v2-14-09ecbc0a05ce@oss.qualcomm.com> (raw)
In-Reply-To: <20250514-topic-ubwc_central-v2-0-09ecbc0a05ce@oss.qualcomm.com>
From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Make the values a bit more meaningful.
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
drivers/soc/qcom/ubwc_config.c | 33 +++++++++++++++++++++------------
include/linux/soc/qcom/ubwc.h | 2 ++
2 files changed, 23 insertions(+), 12 deletions(-)
diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c
index 96b94cf01218cce2dacdba22c7573ba6148fcdd1..06ddf78eb08d31bcdd11f23dcf9ff32e390d2eff 100644
--- a/drivers/soc/qcom/ubwc_config.c
+++ b/drivers/soc/qcom/ubwc_config.c
@@ -32,7 +32,7 @@ static const struct qcom_ubwc_cfg_data qcm2290_data = {
static const struct qcom_ubwc_cfg_data sa8775p_data = {
.ubwc_enc_version = UBWC_4_0,
.ubwc_dec_version = UBWC_4_0,
- .ubwc_swizzle = 4,
+ .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL(3),
.ubwc_bank_spread = true,
.highest_bank_bit = 13,
.macrotile_mode = true,
@@ -41,7 +41,8 @@ static const struct qcom_ubwc_cfg_data sa8775p_data = {
static const struct qcom_ubwc_cfg_data sar2130p_data = {
.ubwc_enc_version = UBWC_3_0, /* 4.0.2 in hw */
.ubwc_dec_version = UBWC_4_3,
- .ubwc_swizzle = 6,
+ .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL(2) |
+ UBWC_SWIZZLE_ENABLE_LVL(3),
.ubwc_bank_spread = true,
.highest_bank_bit = 13,
.macrotile_mode = true,
@@ -50,7 +51,8 @@ static const struct qcom_ubwc_cfg_data sar2130p_data = {
static const struct qcom_ubwc_cfg_data sc7180_data = {
.ubwc_enc_version = UBWC_2_0,
.ubwc_dec_version = UBWC_2_0,
- .ubwc_swizzle = 6,
+ .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL(2) |
+ UBWC_SWIZZLE_ENABLE_LVL(3),
.ubwc_bank_spread = true,
.highest_bank_bit = 14,
};
@@ -58,7 +60,8 @@ static const struct qcom_ubwc_cfg_data sc7180_data = {
static const struct qcom_ubwc_cfg_data sc7280_data = {
.ubwc_enc_version = UBWC_3_0,
.ubwc_dec_version = UBWC_4_0,
- .ubwc_swizzle = 6,
+ .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL(2) |
+ UBWC_SWIZZLE_ENABLE_LVL(3),
.ubwc_bank_spread = true,
.highest_bank_bit = 14,
.macrotile_mode = true,
@@ -74,7 +77,8 @@ static const struct qcom_ubwc_cfg_data sc8180x_data = {
static const struct qcom_ubwc_cfg_data sc8280xp_data = {
.ubwc_enc_version = UBWC_4_0,
.ubwc_dec_version = UBWC_4_0,
- .ubwc_swizzle = 6,
+ .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL(2) |
+ UBWC_SWIZZLE_ENABLE_LVL(3),
.ubwc_bank_spread = true,
.highest_bank_bit = 16,
.macrotile_mode = true,
@@ -95,7 +99,7 @@ static const struct qcom_ubwc_cfg_data sdm845_data = {
static const struct qcom_ubwc_cfg_data sm6115_data = {
.ubwc_enc_version = UBWC_1_0,
.ubwc_dec_version = UBWC_2_0,
- .ubwc_swizzle = 7,
+ .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_ALL,
.ubwc_bank_spread = true,
.highest_bank_bit = 14,
};
@@ -103,7 +107,7 @@ static const struct qcom_ubwc_cfg_data sm6115_data = {
static const struct qcom_ubwc_cfg_data sm6125_data = {
.ubwc_enc_version = UBWC_1_0,
.ubwc_dec_version = UBWC_3_0,
- .ubwc_swizzle = 7,
+ .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_ALL,
.highest_bank_bit = 14,
};
@@ -116,7 +120,8 @@ static const struct qcom_ubwc_cfg_data sm6150_data = {
static const struct qcom_ubwc_cfg_data sm6350_data = {
.ubwc_enc_version = UBWC_2_0,
.ubwc_dec_version = UBWC_2_0,
- .ubwc_swizzle = 6,
+ .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL(2) |
+ UBWC_SWIZZLE_ENABLE_LVL(3),
.ubwc_bank_spread = true,
.highest_bank_bit = 14,
};
@@ -136,7 +141,8 @@ static const struct qcom_ubwc_cfg_data sm8150_data = {
static const struct qcom_ubwc_cfg_data sm8250_data = {
.ubwc_enc_version = UBWC_4_0,
.ubwc_dec_version = UBWC_4_0,
- .ubwc_swizzle = 6,
+ .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL(2) |
+ UBWC_SWIZZLE_ENABLE_LVL(3),
.ubwc_bank_spread = true,
/* TODO: highest_bank_bit = 15 for LP_DDR4 */
.highest_bank_bit = 16,
@@ -146,7 +152,8 @@ static const struct qcom_ubwc_cfg_data sm8250_data = {
static const struct qcom_ubwc_cfg_data sm8350_data = {
.ubwc_enc_version = UBWC_4_0,
.ubwc_dec_version = UBWC_4_0,
- .ubwc_swizzle = 6,
+ .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL(2) |
+ UBWC_SWIZZLE_ENABLE_LVL(3),
.ubwc_bank_spread = true,
/* TODO: highest_bank_bit = 15 for LP_DDR4 */
.highest_bank_bit = 16,
@@ -156,7 +163,8 @@ static const struct qcom_ubwc_cfg_data sm8350_data = {
static const struct qcom_ubwc_cfg_data sm8550_data = {
.ubwc_enc_version = UBWC_4_0,
.ubwc_dec_version = UBWC_4_3,
- .ubwc_swizzle = 6,
+ .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL(2) |
+ UBWC_SWIZZLE_ENABLE_LVL(3),
.ubwc_bank_spread = true,
/* TODO: highest_bank_bit = 15 for LP_DDR4 */
.highest_bank_bit = 16,
@@ -166,7 +174,8 @@ static const struct qcom_ubwc_cfg_data sm8550_data = {
static const struct qcom_ubwc_cfg_data x1e80100_data = {
.ubwc_enc_version = UBWC_4_0,
.ubwc_dec_version = UBWC_4_3,
- .ubwc_swizzle = 6,
+ .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL(2) |
+ UBWC_SWIZZLE_ENABLE_LVL(3),
.ubwc_bank_spread = true,
/* TODO: highest_bank_bit = 15 for LP_DDR4 */
.highest_bank_bit = 16,
diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h
index 30d9744c5d2e06d4aa93b64f7d2bc0e855c7a10b..2a12e054ec62ae7e76c3f3291d6963da726eee4f 100644
--- a/include/linux/soc/qcom/ubwc.h
+++ b/include/linux/soc/qcom/ubwc.h
@@ -26,6 +26,8 @@ struct qcom_ubwc_cfg_data {
* controls level 2, and BIT(2) enables level 3.
*/
u32 ubwc_swizzle;
+#define UBWC_SWIZZLE_ENABLE_ALL GENMASK(2, 0)
+#define UBWC_SWIZZLE_ENABLE_LVL(n) BIT(((n) - 1))
/**
* @highest_bank_bit: Highest Bank Bit
--
2.49.0
next prev parent reply other threads:[~2025-05-14 15:11 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-14 15:10 [RFT PATCH v2 00/15] Add a single source of truth for UBWC configuration data Konrad Dybcio
2025-05-14 15:10 ` [PATCH RFT v2 01/15] soc: qcom: Add UBWC config provider Konrad Dybcio
2025-05-14 15:29 ` Konrad Dybcio
2025-05-14 19:03 ` Dmitry Baryshkov
2025-05-15 15:50 ` Konrad Dybcio
2025-05-14 15:10 ` [PATCH RFT v2 02/15] drm/msm: Offset MDSS HBB value by 13 Konrad Dybcio
2025-05-14 19:04 ` Dmitry Baryshkov
2025-05-14 15:10 ` [PATCH RFT v2 03/15] drm/msm: Use the central UBWC config database Konrad Dybcio
2025-05-14 19:05 ` Dmitry Baryshkov
2025-05-15 10:32 ` kernel test robot
2025-05-14 15:10 ` [PATCH RFT v2 04/15] drm/msm/a6xx: Get a handle to the common UBWC config Konrad Dybcio
2025-05-14 15:10 ` [PATCH RFT v2 05/15] drm/msm/a6xx: Resolve the meaning of AMSBC Konrad Dybcio
2025-05-14 19:16 ` Dmitry Baryshkov
2025-05-14 15:10 ` [PATCH RFT v2 06/15] drm/msm/a6xx: Simplify uavflagprd_inv detection Konrad Dybcio
2025-05-14 19:14 ` Dmitry Baryshkov
2025-05-14 15:10 ` [PATCH RFT v2 07/15] drm/msm/a6xx: Resolve the meaning of UBWC_MODE Konrad Dybcio
2025-05-14 19:14 ` Dmitry Baryshkov
2025-05-14 20:02 ` Rob Clark
2025-05-14 15:10 ` [PATCH RFT v2 08/15] drm/msm/a6xx: Replace '2' with BIT(1) in level2_swizzling_dis calc Konrad Dybcio
2025-05-14 19:15 ` Dmitry Baryshkov
2025-05-14 15:10 ` [PATCH RFT v2 09/15] drm/msm/a6xx: Resolve the meaning of rgb565_predicator Konrad Dybcio
2025-05-14 19:15 ` Dmitry Baryshkov
2025-05-14 15:10 ` [PATCH RFT v2 10/15] drm/msm/a6xx: Simplify min_acc_len calculation Konrad Dybcio
2025-05-14 19:19 ` Dmitry Baryshkov
2025-05-15 15:51 ` Konrad Dybcio
2025-05-14 15:10 ` [PATCH RFT v2 11/15] drm/msm/adreno: Switch to the common UBWC config struct Konrad Dybcio
2025-05-14 19:22 ` Dmitry Baryshkov
2025-05-15 15:51 ` Konrad Dybcio
2025-05-14 15:10 ` [PATCH RFT v2 12/15] drm/msm/a6xx: Drop cfg->ubwc_swizzle override Konrad Dybcio
2025-05-14 20:32 ` Dmitry Baryshkov
2025-05-15 15:52 ` Konrad Dybcio
2025-05-14 15:10 ` [PATCH RFT v2 13/15] soc: qcom: ubwc: Fix SM6125's ubwc_swizzle value Konrad Dybcio
2025-05-14 19:23 ` Dmitry Baryshkov
2025-05-14 20:05 ` Konrad Dybcio
2025-05-14 20:33 ` Dmitry Baryshkov
2025-05-15 16:18 ` Konrad Dybcio
2025-05-15 16:21 ` Dmitry Baryshkov
2025-05-15 16:35 ` Konrad Dybcio
2025-05-15 17:15 ` Dmitry Baryshkov
2025-05-15 17:56 ` Konrad Dybcio
2025-05-15 17:58 ` Dmitry Baryshkov
2025-05-14 15:10 ` Konrad Dybcio [this message]
2025-05-14 19:24 ` [PATCH RFT v2 14/15] soc: qcom: ubwc: Add #defines for UBWC swizzle bits Dmitry Baryshkov
2025-05-14 20:09 ` Konrad Dybcio
2025-05-14 20:33 ` Dmitry Baryshkov
2025-05-14 15:10 ` [PATCH RFC RFT v2 15/15] drm/msm/a6xx: Warn if the highest_bank_bit value is overwritten Konrad Dybcio
2025-05-14 19:25 ` Dmitry Baryshkov
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