[PATCH 0/2] Add support to configure irq coalescing count and delay for AXI DMA

[PATCH 0/2] Add support to configure irq coalescing count and delay for AXI DMA

[Suraj Gupta]

Allow AXI DMA client to configure / report coalesce parameters. Client can
fine-tune irq coalescing parameters based on the transfer load.

AXI ethernet driver uses AXI DMA dmaengine driver. Corresponding changes
for AXI ethernet driver to allow irq coalescing configuration / reporting
via ethtool will be sent to net-next with following subject:
"net: xilinx: axienet: Configure and report coalesce parameters in
DMAengine flow"

Suraj Gupta (2):
  dmaengine: Add support to configure and read IRQ coalescing parameters
  dmaengine: xilinx_dma: Add support to configure/report coalesce
    parameters from/to client using AXI DMA

 drivers/dma/xilinx/xilinx_dma.c | 62 ++++++++++++++++++++++++++++-----
 include/linux/dmaengine.h       | 10 ++++++
 2 files changed, 64 insertions(+), 8 deletions(-)

-- 
2.25.1

[PATCH 1/2] dmaengine: Add support to configure and read IRQ coalescing parameters

[Suraj Gupta]

Interrupt coalescing is a mechanism to reduce the number of hardware
interrupts triggered ether until a certain amount of work is pending,
or a timeout timer triggers. Tuning the interrupt coalesce settings
involves adjusting the amount of work and timeout delay.
Many DMA controllers support to configure coalesce count and delay.
Add support to configure them via dma_slave_config and read
using dma_slave_caps.

Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
---
 include/linux/dmaengine.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index bb146c5ac3e4..c7c1adb8e571 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -431,6 +431,9 @@ enum dma_slave_buswidth {
  * @peripheral_config: peripheral configuration for programming peripheral
  * for dmaengine transfer
  * @peripheral_size: peripheral configuration buffer size
+ * @coalesce_cnt: Maximum number of transfers before receiving an interrupt.
+ * @coalesce_usecs: How many usecs to delay an interrupt after a transfer
+ * is completed.
  *
  * This struct is passed in as configuration data to a DMA engine
  * in order to set up a certain channel for DMA transport at runtime.
@@ -457,6 +460,8 @@ struct dma_slave_config {
 	bool device_fc;
 	void *peripheral_config;
 	size_t peripheral_size;
+	u32 coalesce_cnt;
+	u32 coalesce_usecs;
 };
 
 /**
@@ -507,6 +512,9 @@ enum dma_residue_granularity {
  * @residue_granularity: granularity of the reported transfer residue
  * @descriptor_reuse: if a descriptor can be reused by client and
  * resubmitted multiple times
+ * @coalesce_cnt: Maximum number of transfers before receiving an interrupt.
+ * @coalesce_usecs: How many usecs to delay an interrupt after a transfer
+ * is completed.
  */
 struct dma_slave_caps {
 	u32 src_addr_widths;
@@ -520,6 +528,8 @@ struct dma_slave_caps {
 	bool cmd_terminate;
 	enum dma_residue_granularity residue_granularity;
 	bool descriptor_reuse;
+	u32 coalesce_cnt;
+	u32 coalesce_usecs;
 };
 
 static inline const char *dma_chan_name(struct dma_chan *chan)
-- 
2.25.1

[PATCH 2/2] dmaengine: xilinx_dma: Add support to configure/report coalesce parameters from/to client using AXI DMA

[Suraj Gupta]

AXI DMA supports interrupt coalescing. Client can fine-tune coalesce
parameters based on transaction load. Add support to configure/
report coalesce parameters.
Change delay setting to scale with SG clock rate rather than being a
fixed number of clock cycles (Referred from AXI ethernet driver).

Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
---
 drivers/dma/xilinx/xilinx_dma.c | 62 ++++++++++++++++++++++++++++-----
 1 file changed, 54 insertions(+), 8 deletions(-)

diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index a34d8f0ceed8..b03975b6f00f 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -159,6 +159,9 @@
 		 XILINX_DMA_DMASR_SOF_EARLY_ERR | \
 		 XILINX_DMA_DMASR_DMA_INT_ERR)
 
+/* Constant to convert delay counts to microseconds */
+#define XILINX_DMA_DELAY_SCALE		(125ULL * USEC_PER_SEC)
+
 /* Axi VDMA Flush on Fsync bits */
 #define XILINX_DMA_FLUSH_S2MM		3
 #define XILINX_DMA_FLUSH_MM2S		2
@@ -403,6 +406,7 @@ struct xilinx_dma_tx_descriptor {
  * @terminating: Check for channel being synchronized by user
  * @tasklet: Cleanup work after irq
  * @config: Device configuration info
+ * @slave_cfg: Device configuration info from Dmaengine
  * @flush_on_fsync: Flush on Frame sync
  * @desc_pendingcount: Descriptor pending count
  * @ext_addr: Indicates 64 bit addressing is supported by dma channel
@@ -442,6 +446,7 @@ struct xilinx_dma_chan {
 	bool terminating;
 	struct tasklet_struct tasklet;
 	struct xilinx_vdma_config config;
+	struct dma_slave_config slave_cfg;
 	bool flush_on_fsync;
 	u32 desc_pendingcount;
 	bool ext_addr;
@@ -1540,7 +1545,9 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
 {
 	struct xilinx_dma_tx_descriptor *head_desc, *tail_desc;
 	struct xilinx_axidma_tx_segment *tail_segment;
-	u32 reg;
+	struct dma_slave_config *slave_cfg = &chan->slave_cfg;
+	u64 clk_rate;
+	u32 reg, usec, timer;
 
 	if (chan->err)
 		return;
@@ -1560,19 +1567,38 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
 
 	reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
 
-	if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) {
-		reg &= ~XILINX_DMA_CR_COALESCE_MAX;
+	reg &= ~XILINX_DMA_CR_COALESCE_MAX;
+	reg  &= ~XILINX_DMA_CR_DELAY_MAX;
+
+	/* Use dma_slave_config if it has valid values */
+	if (slave_cfg->coalesce_cnt &&
+	    slave_cfg->coalesce_cnt <= XILINX_DMA_COALESCE_MAX)
+		reg |= slave_cfg->coalesce_cnt <<
+			XILINX_DMA_CR_COALESCE_SHIFT;
+	else if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX)
 		reg |= chan->desc_pendingcount <<
 				  XILINX_DMA_CR_COALESCE_SHIFT;
-		dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
-	}
+
+	if (slave_cfg->coalesce_usecs <= XILINX_DMA_DMACR_DELAY_MAX)
+		usec = slave_cfg->coalesce_usecs;
+	else
+		usec = chan->irq_delay;
+
+	/* Scale with SG clock rate rather than being a fixed number of
+	 * clock cycles.
+	 * 1 Timeout Interval = 125 * (clock period of SG clock)
+	 */
+	clk_rate = clk_get_rate(chan->xdev->rx_clk);
+	timer = DIV64_U64_ROUND_CLOSEST((u64)usec * clk_rate,
+					XILINX_DMA_DELAY_SCALE);
+	timer = min(timer, FIELD_MAX(XILINX_DMA_DMACR_DELAY_MASK));
+	reg |= timer << XILINX_DMA_CR_DELAY_SHIFT;
+
+	dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
 
 	if (chan->has_sg)
 		xilinx_write(chan, XILINX_DMA_REG_CURDESC,
 			     head_desc->async_tx.phys);
-	reg  &= ~XILINX_DMA_CR_DELAY_MAX;
-	reg  |= chan->irq_delay << XILINX_DMA_CR_DELAY_SHIFT;
-	dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
 
 	xilinx_dma_start(chan);
 
@@ -1703,9 +1729,28 @@ static void xilinx_dma_issue_pending(struct dma_chan *dchan)
 static int xilinx_dma_device_config(struct dma_chan *dchan,
 				    struct dma_slave_config *config)
 {
+	struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
+
+	if (!config->coalesce_cnt ||
+	    config->coalesce_cnt > XILINX_DMA_DMACR_FRAME_COUNT_MAX ||
+	    config->coalesce_usecs > XILINX_DMA_DMACR_DELAY_MAX)
+		return -EINVAL;
+
+	chan->slave_cfg.coalesce_cnt = config->coalesce_cnt;
+	chan->slave_cfg.coalesce_usecs = config->coalesce_usecs;
+
 	return 0;
 }
 
+static void xilinx_dma_device_caps(struct dma_chan *dchan,
+				   struct dma_slave_caps *caps)
+{
+	struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
+
+	caps->coalesce_cnt = chan->slave_cfg.coalesce_cnt;
+	caps->coalesce_usecs = chan->slave_cfg.coalesce_usecs;
+}
+
 /**
  * xilinx_dma_complete_descriptor - Mark the active descriptor as complete
  * @chan : xilinx DMA channel
@@ -3178,6 +3223,7 @@ static int xilinx_dma_probe(struct platform_device *pdev)
 	xdev->common.device_tx_status = xilinx_dma_tx_status;
 	xdev->common.device_issue_pending = xilinx_dma_issue_pending;
 	xdev->common.device_config = xilinx_dma_device_config;
+	xdev->common.device_caps = xilinx_dma_device_caps;
 	if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
 		dma_cap_set(DMA_CYCLIC, xdev->common.cap_mask);
 		xdev->common.device_prep_slave_sg = xilinx_dma_prep_slave_sg;
-- 
2.25.1

Re: [PATCH 2/2] dmaengine: xilinx_dma: Add support to configure/report coalesce parameters from/to client using AXI DMA

[kernel test robot]

Hi Suraj,

kernel test robot noticed the following build errors:

[auto build test ERROR on vkoul-dmaengine/next]
[also build test ERROR on xilinx-xlnx/master soc/for-next linus/master v6.15-rc7 next-20250523]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Suraj-Gupta/dmaengine-Add-support-to-configure-and-read-IRQ-coalescing-parameters/20250525-181817
base:   https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git next
patch link:    https://lore.kernel.org/r/20250525101617.1168991-3-suraj.gupta2%40amd.com
patch subject: [PATCH 2/2] dmaengine: xilinx_dma: Add support to configure/report coalesce parameters from/to client using AXI DMA
config: i386-buildonly-randconfig-004-20250525 (https://download.01.org/0day-ci/archive/20250525/202505252153.Nm1BzFUq-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250525/202505252153.Nm1BzFUq-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202505252153.Nm1BzFUq-lkp@intel.com/

All errors (new ones prefixed by >>):

   In file included from include/linux/kernel.h:28,
                    from include/linux/cpumask.h:11,
                    from include/linux/smp.h:13,
                    from include/linux/lockdep.h:14,
                    from include/linux/spinlock.h:63,
                    from include/linux/mmzone.h:8,
                    from include/linux/gfp.h:7,
                    from include/linux/mm.h:7,
                    from include/linux/scatterlist.h:8,
                    from include/linux/dmapool.h:14,
                    from drivers/dma/xilinx/xilinx_dma.c:37:
   drivers/dma/xilinx/xilinx_dma.c: In function 'xilinx_dma_start_transfer':
>> drivers/dma/xilinx/xilinx_dma.c:1594:28: error: implicit declaration of function 'FIELD_MAX' [-Werror=implicit-function-declaration]
    1594 |         timer = min(timer, FIELD_MAX(XILINX_DMA_DMACR_DELAY_MASK));
         |                            ^~~~~~~~~
   include/linux/minmax.h:92:49: note: in definition of macro '__careful_cmp_once'
      92 |         __auto_type ux = (x); __auto_type uy = (y);     \
         |                                                 ^
   include/linux/minmax.h:105:25: note: in expansion of macro '__careful_cmp'
     105 | #define min(x, y)       __careful_cmp(min, x, y)
         |                         ^~~~~~~~~~~~~
   drivers/dma/xilinx/xilinx_dma.c:1594:17: note: in expansion of macro 'min'
    1594 |         timer = min(timer, FIELD_MAX(XILINX_DMA_DMACR_DELAY_MASK));
         |                 ^~~
   In file included from <command-line>:
>> include/linux/compiler_types.h:557:45: error: call to '__compiletime_assert_299' declared with attribute error: min(timer, FIELD_MAX((((int)(sizeof(struct { int:(-!!(__builtin_choose_expr((sizeof(int) == sizeof(*(8 ? ((void *)((long)((24) > (31)) * 0l)) : (int *)8))), (24) > (31), false))); }))) + (((~((0UL))) << (24)) & (~((0UL)) >> (32 - 1 - (31))))))) signedness error
     557 |         _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |                                             ^
   include/linux/compiler_types.h:538:25: note: in definition of macro '__compiletime_assert'
     538 |                         prefix ## suffix();                             \
         |                         ^~~~~~
   include/linux/compiler_types.h:557:9: note: in expansion of macro '_compiletime_assert'
     557 |         _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |         ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/minmax.h:93:9: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      93 |         BUILD_BUG_ON_MSG(!__types_ok(ux, uy),           \
         |         ^~~~~~~~~~~~~~~~
   include/linux/minmax.h:98:9: note: in expansion of macro '__careful_cmp_once'
      98 |         __careful_cmp_once(op, x, y, __UNIQUE_ID(x_), __UNIQUE_ID(y_))
         |         ^~~~~~~~~~~~~~~~~~
   include/linux/minmax.h:105:25: note: in expansion of macro '__careful_cmp'
     105 | #define min(x, y)       __careful_cmp(min, x, y)
         |                         ^~~~~~~~~~~~~
   drivers/dma/xilinx/xilinx_dma.c:1594:17: note: in expansion of macro 'min'
    1594 |         timer = min(timer, FIELD_MAX(XILINX_DMA_DMACR_DELAY_MASK));
         |                 ^~~
   cc1: some warnings being treated as errors
--
   In file included from include/linux/kernel.h:28,
                    from include/linux/cpumask.h:11,
                    from include/linux/smp.h:13,
                    from include/linux/lockdep.h:14,
                    from include/linux/spinlock.h:63,
                    from include/linux/mmzone.h:8,
                    from include/linux/gfp.h:7,
                    from include/linux/mm.h:7,
                    from include/linux/scatterlist.h:8,
                    from include/linux/dmapool.h:14,
                    from xilinx_dma.c:37:
   xilinx_dma.c: In function 'xilinx_dma_start_transfer':
   xilinx_dma.c:1594:28: error: implicit declaration of function 'FIELD_MAX' [-Werror=implicit-function-declaration]
    1594 |         timer = min(timer, FIELD_MAX(XILINX_DMA_DMACR_DELAY_MASK));
         |                            ^~~~~~~~~
   include/linux/minmax.h:92:49: note: in definition of macro '__careful_cmp_once'
      92 |         __auto_type ux = (x); __auto_type uy = (y);     \
         |                                                 ^
   include/linux/minmax.h:105:25: note: in expansion of macro '__careful_cmp'
     105 | #define min(x, y)       __careful_cmp(min, x, y)
         |                         ^~~~~~~~~~~~~
   xilinx_dma.c:1594:17: note: in expansion of macro 'min'
    1594 |         timer = min(timer, FIELD_MAX(XILINX_DMA_DMACR_DELAY_MASK));
         |                 ^~~
   In file included from <command-line>:
>> include/linux/compiler_types.h:557:45: error: call to '__compiletime_assert_299' declared with attribute error: min(timer, FIELD_MAX((((int)(sizeof(struct { int:(-!!(__builtin_choose_expr((sizeof(int) == sizeof(*(8 ? ((void *)((long)((24) > (31)) * 0l)) : (int *)8))), (24) > (31), false))); }))) + (((~((0UL))) << (24)) & (~((0UL)) >> (32 - 1 - (31))))))) signedness error
     557 |         _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |                                             ^
   include/linux/compiler_types.h:538:25: note: in definition of macro '__compiletime_assert'
     538 |                         prefix ## suffix();                             \
         |                         ^~~~~~
   include/linux/compiler_types.h:557:9: note: in expansion of macro '_compiletime_assert'
     557 |         _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
         |         ^~~~~~~~~~~~~~~~~~~
   include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
      39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
         |                                     ^~~~~~~~~~~~~~~~~~
   include/linux/minmax.h:93:9: note: in expansion of macro 'BUILD_BUG_ON_MSG'
      93 |         BUILD_BUG_ON_MSG(!__types_ok(ux, uy),           \
         |         ^~~~~~~~~~~~~~~~
   include/linux/minmax.h:98:9: note: in expansion of macro '__careful_cmp_once'
      98 |         __careful_cmp_once(op, x, y, __UNIQUE_ID(x_), __UNIQUE_ID(y_))
         |         ^~~~~~~~~~~~~~~~~~
   include/linux/minmax.h:105:25: note: in expansion of macro '__careful_cmp'
     105 | #define min(x, y)       __careful_cmp(min, x, y)
         |                         ^~~~~~~~~~~~~
   xilinx_dma.c:1594:17: note: in expansion of macro 'min'
    1594 |         timer = min(timer, FIELD_MAX(XILINX_DMA_DMACR_DELAY_MASK));
         |                 ^~~
   cc1: some warnings being treated as errors


vim +/FIELD_MAX +1594 drivers/dma/xilinx/xilinx_dma.c

  1539	
  1540	/**
  1541	 * xilinx_dma_start_transfer - Starts DMA transfer
  1542	 * @chan: Driver specific channel struct pointer
  1543	 */
  1544	static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
  1545	{
  1546		struct xilinx_dma_tx_descriptor *head_desc, *tail_desc;
  1547		struct xilinx_axidma_tx_segment *tail_segment;
  1548		struct dma_slave_config *slave_cfg = &chan->slave_cfg;
  1549		u64 clk_rate;
  1550		u32 reg, usec, timer;
  1551	
  1552		if (chan->err)
  1553			return;
  1554	
  1555		if (list_empty(&chan->pending_list))
  1556			return;
  1557	
  1558		if (!chan->idle)
  1559			return;
  1560	
  1561		head_desc = list_first_entry(&chan->pending_list,
  1562					     struct xilinx_dma_tx_descriptor, node);
  1563		tail_desc = list_last_entry(&chan->pending_list,
  1564					    struct xilinx_dma_tx_descriptor, node);
  1565		tail_segment = list_last_entry(&tail_desc->segments,
  1566					       struct xilinx_axidma_tx_segment, node);
  1567	
  1568		reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
  1569	
  1570		reg &= ~XILINX_DMA_CR_COALESCE_MAX;
  1571		reg  &= ~XILINX_DMA_CR_DELAY_MAX;
  1572	
  1573		/* Use dma_slave_config if it has valid values */
  1574		if (slave_cfg->coalesce_cnt &&
  1575		    slave_cfg->coalesce_cnt <= XILINX_DMA_COALESCE_MAX)
  1576			reg |= slave_cfg->coalesce_cnt <<
  1577				XILINX_DMA_CR_COALESCE_SHIFT;
  1578		else if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX)
  1579			reg |= chan->desc_pendingcount <<
  1580					  XILINX_DMA_CR_COALESCE_SHIFT;
  1581	
  1582		if (slave_cfg->coalesce_usecs <= XILINX_DMA_DMACR_DELAY_MAX)
  1583			usec = slave_cfg->coalesce_usecs;
  1584		else
  1585			usec = chan->irq_delay;
  1586	
  1587		/* Scale with SG clock rate rather than being a fixed number of
  1588		 * clock cycles.
  1589		 * 1 Timeout Interval = 125 * (clock period of SG clock)
  1590		 */
  1591		clk_rate = clk_get_rate(chan->xdev->rx_clk);
  1592		timer = DIV64_U64_ROUND_CLOSEST((u64)usec * clk_rate,
  1593						XILINX_DMA_DELAY_SCALE);
> 1594		timer = min(timer, FIELD_MAX(XILINX_DMA_DMACR_DELAY_MASK));
  1595		reg |= timer << XILINX_DMA_CR_DELAY_SHIFT;
  1596	
  1597		dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
  1598	
  1599		if (chan->has_sg)
  1600			xilinx_write(chan, XILINX_DMA_REG_CURDESC,
  1601				     head_desc->async_tx.phys);
  1602	
  1603		xilinx_dma_start(chan);
  1604	
  1605		if (chan->err)
  1606			return;
  1607	
  1608		/* Start the transfer */
  1609		if (chan->has_sg) {
  1610			if (chan->cyclic)
  1611				xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
  1612					     chan->cyclic_seg_v->phys);
  1613			else
  1614				xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
  1615					     tail_segment->phys);
  1616		} else {
  1617			struct xilinx_axidma_tx_segment *segment;
  1618			struct xilinx_axidma_desc_hw *hw;
  1619	
  1620			segment = list_first_entry(&head_desc->segments,
  1621						   struct xilinx_axidma_tx_segment,
  1622						   node);
  1623			hw = &segment->hw;
  1624	
  1625			xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR,
  1626				     xilinx_prep_dma_addr_t(hw->buf_addr));
  1627	
  1628			/* Start the transfer */
  1629			dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
  1630				       hw->control & chan->xdev->max_buffer_len);
  1631		}
  1632	
  1633		list_splice_tail_init(&chan->pending_list, &chan->active_list);
  1634		chan->desc_pendingcount = 0;
  1635		chan->idle = false;
  1636	}
  1637	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki