From: "Clément Léger" <cleger@rivosinc.com>
To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: "Clément Léger" <cleger@rivosinc.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Alexandre Ghiti" <alex@ghiti.fr>
Subject: [PATCH 1/2] riscv: process: use unsigned int instead of unsigned long for put_user()
Date: Fri, 30 May 2025 22:56:57 +0200 [thread overview]
Message-ID: <20250530205658.624195-2-cleger@rivosinc.com> (raw)
In-Reply-To: <20250530205658.624195-1-cleger@rivosinc.com>
The specification of prctl() for GET_UNALIGN_CTL states that the value is
returned in an unsigned int * address passed as an unsigned long. Change
the type to match that and avoid an unaligned access as well.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
arch/riscv/kernel/process.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c
index 15d8f75902f8..9ee6d816b98b 100644
--- a/arch/riscv/kernel/process.c
+++ b/arch/riscv/kernel/process.c
@@ -57,7 +57,7 @@ int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
if (!unaligned_ctl_available())
return -EINVAL;
- return put_user(tsk->thread.align_ctl, (unsigned long __user *)adr);
+ return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
}
void __show_regs(struct pt_regs *regs)
--
2.49.0
next prev parent reply other threads:[~2025-05-30 20:57 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-30 20:56 [PATCH 0/2] riscv: misaligned: fix misaligned accesses handling in put/get_user() Clément Léger
2025-05-30 20:56 ` Clément Léger [this message]
2025-05-31 12:29 ` [PATCH 1/2] riscv: process: use unsigned int instead of unsigned long for put_user() Alexandre Ghiti
2025-05-30 20:56 ` [PATCH 2/2] riscv: uaccess: do not do misaligned accesses in get/put_user() Clément Léger
2025-05-31 12:35 ` Alexandre Ghiti
2025-06-02 7:37 ` Clément Léger
2025-06-02 15:22 ` Alexandre Ghiti
2025-05-31 18:28 ` David Laight
2025-06-01 17:35 ` Maciej W. Rozycki
2025-06-02 7:35 ` Clément Léger
2025-06-02 7:34 ` Clément Léger
2025-05-31 13:32 ` [PATCH 0/2] riscv: misaligned: fix misaligned accesses handling in put/get_user() Alexandre Ghiti
2025-06-02 7:19 ` Clément Léger
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