[PATCH v1] arm64: dts: freescale: imx8mp-var-som: Add EQoS support with MaxLinear PHY

[PATCH v1] arm64: dts: freescale: imx8mp-var-som: Add EQoS support with MaxLinear PHY

[Stefano Radaelli]

Enable the EQoS Ethernet controller on the i.MX8MP VAR-SOM with the
integrated Maxlinear MXL86110 PHY. The PHY is connected to the EQOS
MDIO bus at address 4.

This patch adds:
- EQOS controller configuration with RGMII interface.
- Proper reset timings.
- PHY power supply regulators.
- RGMII pinmux configuration for all data, control and clock signals.
- LED configuration for link status indication via the LED subsystem
  under /sys/class/leds/, leveraging the support implemented in the.
  mxl86110 PHY driver (drivers/net/phy/mxl-86110.c).
  Two LEDs are defined to match the LED configuration on the Variscite
  VAR-SOM Carrier Boards:
    * LED@0: Yellow, netdev trigger.
    * LED@1: Green, netdev trigger.

The RGMII TX/RX delays are implemented in SOM via PCB passive
delays, so no software delay configuration is required.

Signed-off-by: Stefano Radaelli <stefano.radaelli21@gmail.com>
---
 .../boot/dts/freescale/imx8mp-var-som.dtsi    | 87 +++++++++++++++++++
 1 file changed, 87 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi
index b59da91fdd04..3be59692849f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi
@@ -55,6 +55,24 @@ reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
 		states = <3300000 0x0 1800000 0x1>;
 		vin-supply = <&ldo5>;
 	};
+
+	reg_phy_supply: regulator-phy-supply {
+		compatible = "regulator-fixed";
+		regulator-name = "phy-supply";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-enable-ramp-delay = <20000>;
+		gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-always-on;
+	};
+
+	reg_phy_vddio: regulator-phy-vddio {
+		compatible = "regulator-fixed";
+		regulator-name = "vddio-1v8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
 };
 
 &A53_0 {
@@ -73,6 +91,54 @@ &A53_3 {
 	cpu-supply = <&buck2>;
 };
 
+&eqos {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_eqos>;
+	/*
+	 * The required RGMII TX and RX 2ns delays are implemented directly
+	 * in hardware via passive delay elements on the SOM PCB.
+	 * No delay configuration is needed in software via PHY driver.
+	 */
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy0>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@4 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <4>;
+			at803x,eee-disabled;
+			eee-broken-1000t;
+			reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <10000>;
+			reset-deassert-us = <100000>;
+			vddio-supply = <&reg_phy_vddio>;
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					color = <LED_COLOR_ID_YELLOW>;
+					function = LED_FUNCTION_LAN;
+					linux,default-trigger = "netdev";
+				};
+
+				led@1 {
+					reg = <1>;
+					color = <LED_COLOR_ID_GREEN>;
+					function = LED_FUNCTION_LAN;
+					linux,default-trigger = "netdev";
+				};
+			};
+		};
+	};
+};
+
 &i2c1 {
 	clock-frequency = <400000>;
 	pinctrl-names = "default";
@@ -239,6 +305,27 @@ &wdog1 {
 
 &iomuxc {
 
+	pinctrl_eqos: eqosgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x2
+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x2
+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x90
+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x90
+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x90
+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x90
+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90
+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x90
+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x16
+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x16
+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x16
+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x16
+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x16
+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16
+			MX8MP_IOMUXC_SD2_WP__GPIO2_IO20					0x10
+			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10				0x150
+		>;
+	};
+
 	pinctrl_i2c1: i2c1grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_SD1_DATA4__I2C1_SCL				0x400001c2

base-commit: e271ed52b344ac02d4581286961d0c40acc54c03
prerequisite-patch-id: 2335ebcc90360b008c840e7edf7e34a595880edf
-- 
2.43.0

Re: [PATCH v1] arm64: dts: freescale: imx8mp-var-som: Add EQoS support with MaxLinear PHY

[Frank Li]

On Mon, Jun 09, 2025 at 04:06:42PM +0200, Stefano Radaelli wrote:
> Enable the EQoS Ethernet controller on the i.MX8MP VAR-SOM with the
> integrated Maxlinear MXL86110 PHY. The PHY is connected to the EQOS
> MDIO bus at address 4.
>
> This patch adds:
> - EQOS controller configuration with RGMII interface.
> - Proper reset timings.
> - PHY power supply regulators.
> - RGMII pinmux configuration for all data, control and clock signals.
> - LED configuration for link status indication via the LED subsystem
>   under /sys/class/leds/, leveraging the support implemented in the.
>   mxl86110 PHY driver (drivers/net/phy/mxl-86110.c).
>   Two LEDs are defined to match the LED configuration on the Variscite
>   VAR-SOM Carrier Boards:
>     * LED@0: Yellow, netdev trigger.
>     * LED@1: Green, netdev trigger.
>
> The RGMII TX/RX delays are implemented in SOM via PCB passive
> delays, so no software delay configuration is required.
>
> Signed-off-by: Stefano Radaelli <stefano.radaelli21@gmail.com>
> ---
>  .../boot/dts/freescale/imx8mp-var-som.dtsi    | 87 +++++++++++++++++++
>  1 file changed, 87 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi
> index b59da91fdd04..3be59692849f 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi
> @@ -55,6 +55,24 @@ reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
>  		states = <3300000 0x0 1800000 0x1>;
>  		vin-supply = <&ldo5>;
>  	};
> +
> +	reg_phy_supply: regulator-phy-supply {
> +		compatible = "regulator-fixed";
> +		regulator-name = "phy-supply";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		regulator-enable-ramp-delay = <20000>;
> +		gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
> +		enable-active-high;
> +		regulator-always-on;
> +	};
> +
> +	reg_phy_vddio: regulator-phy-vddio {
> +		compatible = "regulator-fixed";
> +		regulator-name = "vddio-1v8";
> +		regulator-min-microvolt = <1800000>;
> +		regulator-max-microvolt = <1800000>;
> +	};
>  };
>
>  &A53_0 {
> @@ -73,6 +91,54 @@ &A53_3 {
>  	cpu-supply = <&buck2>;
>  };
>
> +&eqos {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_eqos>;
> +	/*
> +	 * The required RGMII TX and RX 2ns delays are implemented directly
> +	 * in hardware via passive delay elements on the SOM PCB.
> +	 * No delay configuration is needed in software via PHY driver.
> +	 */
> +	phy-mode = "rgmii";
> +	phy-handle = <&ethphy0>;
> +	status = "okay";
> +
> +	mdio {
> +		compatible = "snps,dwmac-mdio";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		ethphy0: ethernet-phy@4 {
> +			compatible = "ethernet-phy-ieee802.3-c22";
> +			reg = <4>;
> +			at803x,eee-disabled;
> +			eee-broken-1000t;

are you sure eee broken? recently we found it wrong copy from fec.


> +			reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
> +			reset-assert-us = <10000>;
> +			reset-deassert-us = <100000>;
> +			vddio-supply = <&reg_phy_vddio>;

extra empty line here.

Frank
> +			leds {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				led@0 {
> +					reg = <0>;
> +					color = <LED_COLOR_ID_YELLOW>;
> +					function = LED_FUNCTION_LAN;
> +					linux,default-trigger = "netdev";
> +				};
> +
> +				led@1 {
> +					reg = <1>;
> +					color = <LED_COLOR_ID_GREEN>;
> +					function = LED_FUNCTION_LAN;
> +					linux,default-trigger = "netdev";
> +				};
> +			};
> +		};
> +	};
> +};
> +
>  &i2c1 {
>  	clock-frequency = <400000>;
>  	pinctrl-names = "default";
> @@ -239,6 +305,27 @@ &wdog1 {
>
>  &iomuxc {
>
> +	pinctrl_eqos: eqosgrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x2
> +			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x2
> +			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x90
> +			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x90
> +			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x90
> +			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x90
> +			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90
> +			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x90
> +			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x16
> +			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x16
> +			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x16
> +			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x16
> +			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x16
> +			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16
> +			MX8MP_IOMUXC_SD2_WP__GPIO2_IO20					0x10
> +			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10				0x150
> +		>;
> +	};
> +
>  	pinctrl_i2c1: i2c1grp {
>  		fsl,pins = <
>  			MX8MP_IOMUXC_SD1_DATA4__I2C1_SCL				0x400001c2
>
> base-commit: e271ed52b344ac02d4581286961d0c40acc54c03
> prerequisite-patch-id: 2335ebcc90360b008c840e7edf7e34a595880edf
> --
> 2.43.0
>

Re: [PATCH v1] arm64: dts: freescale: imx8mp-var-som: Add EQoS support with MaxLinear PHY

[Andrew Lunn]

On Mon, Jun 09, 2025 at 04:06:42PM +0200, Stefano Radaelli wrote:
> Enable the EQoS Ethernet controller on the i.MX8MP VAR-SOM with the
> integrated Maxlinear MXL86110 PHY. The PHY is connected to the EQOS
> MDIO bus at address 4.

> +		ethphy0: ethernet-phy@4 {
> +			compatible = "ethernet-phy-ieee802.3-c22";
> +			reg = <4>;
> +			at803x,eee-disabled;
> +			eee-broken-1000t;

The commit message says it is a Maxlinear. So at803x vendor properties
are not relevant here.

    Andrew

Re: [PATCH v1] arm64: dts: freescale: imx8mp-var-som: Add EQoS support with MaxLinear PHY

[Stefano Radaelli]

Hi Frank,

> +                     reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
> +                     reset-assert-us = <10000>;
> +                     reset-deassert-us = <100000>;
> +                     vddio-supply = <&reg_phy_vddio>;
> extra empty line here.

Ack, will add the empty line before the leds block.

> +                     at803x,eee-disabled;
> +                     eee-broken-1000t;
> are you sure eee broken? recently we found it wrong copy from fec.

You're absolutely right. I checked the MXL86110 datasheet and it clearly states
that EEE is properly supported for both 100BASE-TX and 1000BASE-T operations.
These properties were indeed copied incorrectly from other configurations.
I'll remove both at803x,eee-disabled and eee-broken-1000t properties in v2.

Thanks for catching this!

Il giorno lun 9 giu 2025 alle ore 17:10 Frank Li <Frank.li@nxp.com> ha scritto:
>
> On Mon, Jun 09, 2025 at 04:06:42PM +0200, Stefano Radaelli wrote:
> > Enable the EQoS Ethernet controller on the i.MX8MP VAR-SOM with the
> > integrated Maxlinear MXL86110 PHY. The PHY is connected to the EQOS
> > MDIO bus at address 4.
> >
> > This patch adds:
> > - EQOS controller configuration with RGMII interface.
> > - Proper reset timings.
> > - PHY power supply regulators.
> > - RGMII pinmux configuration for all data, control and clock signals.
> > - LED configuration for link status indication via the LED subsystem
> >   under /sys/class/leds/, leveraging the support implemented in the.
> >   mxl86110 PHY driver (drivers/net/phy/mxl-86110.c).
> >   Two LEDs are defined to match the LED configuration on the Variscite
> >   VAR-SOM Carrier Boards:
> >     * LED@0: Yellow, netdev trigger.
> >     * LED@1: Green, netdev trigger.
> >
> > The RGMII TX/RX delays are implemented in SOM via PCB passive
> > delays, so no software delay configuration is required.
> >
> > Signed-off-by: Stefano Radaelli <stefano.radaelli21@gmail.com>
> > ---
> >  .../boot/dts/freescale/imx8mp-var-som.dtsi    | 87 +++++++++++++++++++
> >  1 file changed, 87 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi
> > index b59da91fdd04..3be59692849f 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi
> > @@ -55,6 +55,24 @@ reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
> >               states = <3300000 0x0 1800000 0x1>;
> >               vin-supply = <&ldo5>;
> >       };
> > +
> > +     reg_phy_supply: regulator-phy-supply {
> > +             compatible = "regulator-fixed";
> > +             regulator-name = "phy-supply";
> > +             regulator-min-microvolt = <3300000>;
> > +             regulator-max-microvolt = <3300000>;
> > +             regulator-enable-ramp-delay = <20000>;
> > +             gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
> > +             enable-active-high;
> > +             regulator-always-on;
> > +     };
> > +
> > +     reg_phy_vddio: regulator-phy-vddio {
> > +             compatible = "regulator-fixed";
> > +             regulator-name = "vddio-1v8";
> > +             regulator-min-microvolt = <1800000>;
> > +             regulator-max-microvolt = <1800000>;
> > +     };
> >  };
> >
> >  &A53_0 {
> > @@ -73,6 +91,54 @@ &A53_3 {
> >       cpu-supply = <&buck2>;
> >  };
> >
> > +&eqos {
> > +     pinctrl-names = "default";
> > +     pinctrl-0 = <&pinctrl_eqos>;
> > +     /*
> > +      * The required RGMII TX and RX 2ns delays are implemented directly
> > +      * in hardware via passive delay elements on the SOM PCB.
> > +      * No delay configuration is needed in software via PHY driver.
> > +      */
> > +     phy-mode = "rgmii";
> > +     phy-handle = <&ethphy0>;
> > +     status = "okay";
> > +
> > +     mdio {
> > +             compatible = "snps,dwmac-mdio";
> > +             #address-cells = <1>;
> > +             #size-cells = <0>;
> > +
> > +             ethphy0: ethernet-phy@4 {
> > +                     compatible = "ethernet-phy-ieee802.3-c22";
> > +                     reg = <4>;
> > +                     at803x,eee-disabled;
> > +                     eee-broken-1000t;
>
> are you sure eee broken? recently we found it wrong copy from fec.
>
>
> > +                     reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
> > +                     reset-assert-us = <10000>;
> > +                     reset-deassert-us = <100000>;
> > +                     vddio-supply = <&reg_phy_vddio>;
>
> extra empty line here.
>
> Frank
> > +                     leds {
> > +                             #address-cells = <1>;
> > +                             #size-cells = <0>;
> > +
> > +                             led@0 {
> > +                                     reg = <0>;
> > +                                     color = <LED_COLOR_ID_YELLOW>;
> > +                                     function = LED_FUNCTION_LAN;
> > +                                     linux,default-trigger = "netdev";
> > +                             };
> > +
> > +                             led@1 {
> > +                                     reg = <1>;
> > +                                     color = <LED_COLOR_ID_GREEN>;
> > +                                     function = LED_FUNCTION_LAN;
> > +                                     linux,default-trigger = "netdev";
> > +                             };
> > +                     };
> > +             };
> > +     };
> > +};
> > +
> >  &i2c1 {
> >       clock-frequency = <400000>;
> >       pinctrl-names = "default";
> > @@ -239,6 +305,27 @@ &wdog1 {
> >
> >  &iomuxc {
> >
> > +     pinctrl_eqos: eqosgrp {
> > +             fsl,pins = <
> > +                     MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC                             0x2
> > +                     MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO                           0x2
> > +                     MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0                       0x90
> > +                     MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1                       0x90
> > +                     MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2                       0x90
> > +                     MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3                       0x90
> > +                     MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK       0x90
> > +                     MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL                 0x90
> > +                     MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0                       0x16
> > +                     MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1                       0x16
> > +                     MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2                       0x16
> > +                     MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3                       0x16
> > +                     MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL                 0x16
> > +                     MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK       0x16
> > +                     MX8MP_IOMUXC_SD2_WP__GPIO2_IO20                                 0x10
> > +                     MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10                             0x150
> > +             >;
> > +     };
> > +
> >       pinctrl_i2c1: i2c1grp {
> >               fsl,pins = <
> >                       MX8MP_IOMUXC_SD1_DATA4__I2C1_SCL                                0x400001c2
> >
> > base-commit: e271ed52b344ac02d4581286961d0c40acc54c03
> > prerequisite-patch-id: 2335ebcc90360b008c840e7edf7e34a595880edf
> > --
> > 2.43.0
> >

Re: [PATCH v1] arm64: dts: freescale: imx8mp-var-som: Add EQoS support with MaxLinear PHY

[Stefano Radaelli]

Hi Andrew,

> +                     at803x,eee-disabled;
> +                     eee-broken-1000t;
> The commit message says it is a Maxlinear. So at803x vendor properties
> are not relevant here.

You're absolutely correct.
The at803x,eee-disabled property is specific to other PHYs and has no meaning
for the Maxlinear MXL86110.
I mistakenly copied this from another configuration without considering the
vendor-specific nature of the property.

Thanks for pointing this out!

Il giorno lun 9 giu 2025 alle ore 17:17 Andrew Lunn <andrew@lunn.ch> ha scritto:
>
> On Mon, Jun 09, 2025 at 04:06:42PM +0200, Stefano Radaelli wrote:
> > Enable the EQoS Ethernet controller on the i.MX8MP VAR-SOM with the
> > integrated Maxlinear MXL86110 PHY. The PHY is connected to the EQOS
> > MDIO bus at address 4.
>
> > +             ethphy0: ethernet-phy@4 {
> > +                     compatible = "ethernet-phy-ieee802.3-c22";
> > +                     reg = <4>;
> > +                     at803x,eee-disabled;
> > +                     eee-broken-1000t;
>
> The commit message says it is a Maxlinear. So at803x vendor properties
> are not relevant here.
>
>     Andrew