From: Steven Rostedt <rostedt@goodmis.org>
To: "Masami Hiramatsu (Google)" <mhiramat@kernel.org>
Cc: Naresh Kamboju <naresh.kamboju@linaro.org>,
open list <linux-kernel@vger.kernel.org>,
Linux trace kernel <linux-trace-kernel@vger.kernel.org>,
lkft-triage@lists.linaro.org,
Stephen Rothwell <sfr@canb.auug.org.au>,
Arnd Bergmann <arnd@arndb.de>,
Dan Carpenter <dan.carpenter@linaro.org>,
Anders Roxell <anders.roxell@linaro.org>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
x86@kernel.org
Subject: Re: next-20250605: Test regression: qemu-x86_64-compat mode ltp tracing Oops int3 kernel panic
Date: Tue, 10 Jun 2025 09:25:23 -0400 [thread overview]
Message-ID: <20250610092523.7be86d1d@gandalf.local.home> (raw)
In-Reply-To: <20250610174136.b88bd16959a4d7eff27cc3fa@kernel.org>
On Tue, 10 Jun 2025 17:41:36 +0900
Masami Hiramatsu (Google) <mhiramat@kernel.org> wrote:
> SERIALIZE instruction may flash pipeline, thus the processor needs
> to reload the instruction. But it is not ensured to reload it from
> memory because SERIALIZE does not invalidate the cache.
From my understanding, an IPI on a CPU is equivalent to a smp_mb() on that
CPU. There shouldn't be any need for flushing the cache.
>
> If that hypotheses is correct, we need to invalidate the cache
> (flush TLB) in the third step, before the do_sync_core().
I'm not sure how the TLB would be affected.
-- Steve
>
> Or, if it is unsure, we can just evacuate the kernel from die("int3")
> by retrying the new instruction, when the INT3 is disappeared.
next prev parent reply other threads:[~2025-06-10 13:23 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-05 11:42 Naresh Kamboju
2025-06-09 13:09 ` Masami Hiramatsu
2025-06-10 8:41 ` Masami Hiramatsu
2025-06-10 13:25 ` Steven Rostedt [this message]
2025-06-10 13:20 ` Naresh Kamboju
2025-06-10 14:43 ` Masami Hiramatsu
2025-06-10 14:47 ` [RFC PATCH 1/2] x86: Retry with new instruction if INT3 is disappaered Masami Hiramatsu (Google)
2025-06-10 14:47 ` [RFC PATCH 2/2] x86: alternative: Invalidate the cache for updated instructions Masami Hiramatsu (Google)
2025-06-10 15:50 ` Steven Rostedt
2025-06-11 0:21 ` Masami Hiramatsu
2025-06-11 10:26 ` Masami Hiramatsu
2025-06-11 14:20 ` Steven Rostedt
2025-06-11 15:42 ` Steven Rostedt
2025-06-12 0:04 ` Masami Hiramatsu
2025-06-11 11:30 ` Peter Zijlstra
2025-06-12 0:17 ` Masami Hiramatsu
2025-06-12 16:24 ` Naresh Kamboju
2025-06-13 3:09 ` Masami Hiramatsu
2025-06-10 14:53 ` next-20250605: Test regression: qemu-x86_64-compat mode ltp tracing Oops int3 kernel panic Steven Rostedt
2025-06-12 13:09 ` Naresh Kamboju
2025-06-13 8:27 ` Masami Hiramatsu
2025-06-13 12:01 ` Masami Hiramatsu
2025-06-16 7:36 ` Masami Hiramatsu
2025-06-17 10:41 ` Masami Hiramatsu
2025-06-17 12:10 ` Naresh Kamboju
2025-06-17 12:25 ` Steven Rostedt
2025-06-17 12:31 ` Naresh Kamboju
2025-06-17 14:29 ` Steven Rostedt
2025-06-17 23:40 ` Masami Hiramatsu
2025-06-19 14:00 ` Steven Rostedt
2025-06-17 16:45 ` Naresh Kamboju
2025-06-17 23:05 ` Masami Hiramatsu
2025-06-17 23:32 ` Steven Rostedt
2025-06-10 0:29 ` Steven Rostedt
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