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From: Jacky Chou <jacky_chou@aspeedtech.com>
To: <bhelgaas@google.com>, <lpieralisi@kernel.org>,
	<kwilczynski@kernel.org>, <mani@kernel.org>, <robh@kernel.org>,
	<krzk+dt@kernel.org>, <conor+dt@kernel.org>, <joel@jms.id.au>,
	<andrew@codeconstruct.com.au>, <vkoul@kernel.org>,
	<kishon@kernel.org>, <linus.walleij@linaro.org>,
	<p.zabel@pengutronix.de>, <linux-aspeed@lists.ozlabs.org>,
	<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <linux-phy@lists.infradead.org>,
	<openbmc@lists.ozlabs.org>, <linux-gpio@vger.kernel.org>
Cc: <elbadrym@google.com>, <romlem@google.com>, <anhphan@google.com>,
	<wak@google.com>, <yuxiaozhang@google.com>,
	<BMC-SW@aspeedtech.com>
Subject: [PATCH 2/7] dt-bindings: pci: Add document for ASPEED PCIe Config
Date: Fri, 13 Jun 2025 11:29:56 +0800	[thread overview]
Message-ID: <20250613033001.3153637-3-jacky_chou@aspeedtech.com> (raw)
In-Reply-To: <20250613033001.3153637-1-jacky_chou@aspeedtech.com>

Add device tree binding documentation for the ASPEED AST2600/AST2700 PCIe
configuration syscon block. This shared register space is used by multiple
PCIe-related devices to coordinate and manage common PCIe settings.
The binding describes the required compatible strings and register space
for the configuration node.

Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
---
 .../bindings/pci/aspeed-pcie-cfg.yaml         | 41 +++++++++++++++++++
 1 file changed, 41 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/aspeed-pcie-cfg.yaml

diff --git a/Documentation/devicetree/bindings/pci/aspeed-pcie-cfg.yaml b/Documentation/devicetree/bindings/pci/aspeed-pcie-cfg.yaml
new file mode 100644
index 000000000000..6b51eedf4c47
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/aspeed-pcie-cfg.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/aspeed-pcie-cfg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ASPEED PCIe Configuration
+
+maintainers:
+  - Jacky Chou <jacky_chou@aspeedtech.com>
+
+description: |
+  The ASPEED PCIe configuration syscon block provides a set of registers shared
+  by multiple PCIe-related devices within the SoC. This node represents the
+  common configuration space that allows these devices to coordinate and manage
+  shared PCIe settings, including address mapping, control, and status
+  registers. The syscon interface enables Linux drivers for various PCIe devices
+  to access  and modify these shared registers in a consistent and centralized
+  manner.
+
+properties:
+  compatible:
+    enum:
+      - aspeed,ast2600-pcie-cfg
+      - aspeed,ast2700-pcie-cfg
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    pcie-cfg@1e770000 {
+      compatible = "aspeed,ast2600-pcie-cfg";
+      reg = <0x1e770000 0x80>;
+    };
-- 
2.43.0


  parent reply	other threads:[~2025-06-13  3:30 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-13  3:29 [PATCH 0/7] Add ASPEED PCIe Root Complex support Jacky Chou
2025-06-13  3:29 ` [PATCH 1/7] dt-bindings: phy: Add document for ASPEED PCIe PHY Jacky Chou
2025-06-13  9:14   ` neil.armstrong
2025-06-20  5:03     ` 回覆: " Jacky Chou
2025-06-13  9:44   ` Krzysztof Kozlowski
2025-06-20  8:29     ` 回覆: " Jacky Chou
2025-06-13  3:29 ` Jacky Chou [this message]
2025-06-13  9:46   ` [PATCH 2/7] dt-bindings: pci: Add document for ASPEED PCIe Config Krzysztof Kozlowski
2025-06-20  8:32     ` 回覆: " Jacky Chou
2025-06-13 15:58   ` Bjorn Helgaas
2025-06-20  5:27     ` Jacky Chou
2025-06-13  3:29 ` [PATCH 3/7] dt-bindings: pci: Add document for ASPEED PCIe RC Jacky Chou
2025-06-13  9:50   ` Krzysztof Kozlowski
2025-06-20  8:36     ` Jacky Chou
2025-06-25 21:04   ` Rob Herring
2025-06-27  9:59     ` 回覆: " Jacky Chou
2025-06-13  3:29 ` [PATCH 4/7] ARM: dts: aspeed-g6: Add AST2600 PCIe RC PERST ctrl pin Jacky Chou
2025-06-13  9:51   ` Krzysztof Kozlowski
2025-06-20  8:36     ` Jacky Chou
2025-06-13 15:59   ` Bjorn Helgaas
2025-06-13  3:29 ` [PATCH 5/7] ARM: dts: aspeed-g6: Add PCIe RC node Jacky Chou
2025-06-13 15:54   ` Bjorn Helgaas
2025-06-20  5:24     ` 回覆: " Jacky Chou
2025-06-24 15:28       ` Bjorn Helgaas
2025-06-25  8:27         ` 回覆: " Jacky Chou
2025-06-25 22:16           ` Bjorn Helgaas
2025-06-27 10:02             ` Jacky Chou
2025-06-13  3:30 ` [PATCH 6/7] pinctrl: aspeed-g6: Add PCIe RC PERST pin group Jacky Chou
2025-06-18 12:15   ` Linus Walleij
2025-06-20  7:09   ` Andrew Jeffery
2025-06-13  3:30 ` [PATCH 7/7] pci: aspeed: Add ASPEED PCIe host controller driver Jacky Chou
2025-06-13  9:54   ` Krzysztof Kozlowski
2025-06-23  2:42     ` 回覆: " Jacky Chou
2025-06-13 12:03   ` Ilpo Järvinen
2025-06-23  5:41     ` Jacky Chou
2025-06-24 10:50       ` Ilpo Järvinen
2025-06-24 11:11         ` 回覆: " Jacky Chou
2025-06-24 15:40       ` Bjorn Helgaas
2025-06-25  8:32         ` 回覆: " Jacky Chou
2025-06-13 16:28   ` Bjorn Helgaas
2025-06-20  6:05     ` 回覆: " Jacky Chou
2025-06-24 15:33       ` Bjorn Helgaas
2025-06-14  2:07   ` kernel test robot
2025-06-19  8:14   ` kernel test robot
2025-06-13  9:18 ` [PATCH 0/7] Add ASPEED PCIe Root Complex support neil.armstrong
2025-06-20  8:20   ` 回覆: " Jacky Chou
2025-06-24  7:29     ` Neil Armstrong
2025-06-24 10:54       ` 回覆: " Jacky Chou
2025-06-16 21:46 ` Rob Herring (Arm)

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