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From: Krzysztof Kozlowski <krzk@kernel.org>
To: Jacky Chou <jacky_chou@aspeedtech.com>,
	bhelgaas@google.com, lpieralisi@kernel.org,
	kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org,
	krzk+dt@kernel.org, conor+dt@kernel.org, joel@jms.id.au,
	andrew@codeconstruct.com.au, vkoul@kernel.org, kishon@kernel.org,
	linus.walleij@linaro.org, p.zabel@pengutronix.de,
	linux-aspeed@lists.ozlabs.org, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org,
	openbmc@lists.ozlabs.org, linux-gpio@vger.kernel.org
Cc: elbadrym@google.com, romlem@google.com, anhphan@google.com,
	wak@google.com, yuxiaozhang@google.com, BMC-SW@aspeedtech.com
Subject: Re: [PATCH 3/7] dt-bindings: pci: Add document for ASPEED PCIe RC
Date: Fri, 13 Jun 2025 11:50:28 +0200	[thread overview]
Message-ID: <b387a2ed-af47-45a9-871e-d43a66e41f21@kernel.org> (raw)
In-Reply-To: <20250613033001.3153637-4-jacky_chou@aspeedtech.com>

On 13/06/2025 05:29, Jacky Chou wrote:
> Add device tree binding documentation for the ASPEED PCIe Root Complex
> controller. This binding describes the required and optional properties
> for configuring the PCIe RC node, including support for syscon phandles,
> MSI, clocks, resets, and interrupt mapping. The schema enforces strict
> property validation and provides a comprehensive example for reference.
> 
> Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
> ---
>  .../devicetree/bindings/pci/aspeed-pcie.yaml  | 159 ++++++++++++++++++
>  1 file changed, 159 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/aspeed-pcie.yaml
> 
> diff --git a/Documentation/devicetree/bindings/pci/aspeed-pcie.yaml b/Documentation/devicetree/bindings/pci/aspeed-pcie.yaml
> new file mode 100644
> index 000000000000..5b50a9e2d472
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/aspeed-pcie.yaml

Same comments.

> @@ -0,0 +1,159 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/aspeed-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ASPEED PCIe Root Complex Controller
> +
> +maintainers:
> +  - Jacky Chou <jacky_chou@aspeedtech.com>
> +
> +description: |

Do not need '|' unless you need to preserve formatting.


> +  Device tree binding for the ASPEED PCIe Root Complex controller.

No, describe the hardware. Your current description is 100% redundant.
It is never useful to say in DT binding description that it is a DT
binding. It cannot be anything else, can it?

> +
> +properties:
> +  compatible:
> +    enum:
> +      - aspeed,ast2600-pcie
> +      - aspeed,ast2700-pcie
> +
> +  device_type:
> +    const: pci

You need to include proper pci schema and drop all redundant properties.

Look at other schemas.

> +
> +  reg:
> +    maxItems: 1
> +
> +  ranges:
> +    minItems: 2
> +    maxItems: 2
> +
> +  interrupts:
> +    description: IntX and MSI interrupt

Need to list the items. Look at other schemas.

> +
> +  resets:
> +    items:
> +      - description: Module reset
> +      - description: PCIe PERST
> +
> +  reset-names:
> +    items:
> +      - const: h2x
> +      - const: perst
> +
> +  msi-parent: true
> +
> +  msi_address:

Where is this property defined?  I do not see in kernel nor in dtschema.
Drop and use existing properties. I am not even talking about coding
style...

> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description: MSI address
> +
> +  aspeed,ahbc:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description: Phandle to ASPEED AHBC syscon.

For what purpose?

> +
> +  aspeed,pciecfg:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description: Phandle to ASPEED PCIe configuration syscon.

For what purpose?

> +
> +  aspeed,pciephy:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description: Phandle to ASPEED PCIe PHY syscon.

For what purpose?

> +
> +  clocks:
> +    description: PCIe BUS clock

Missing constraints.

Just open any other  binding and do not implement things diferently.

> +
> +  interrupt-controller:
> +    description: Interrupt controller node for handling legacy PCI interrupts.
> +    type: object
> +    properties:
> +      '#address-cells':
> +        const: 0
> +      '#interrupt-cells':
> +        const: 1
> +      interrupt-controller: true
> +
> +    required:
> +      - '#address-cells'
> +      - '#interrupt-cells'
> +      - interrupt-controller
> +
> +    additionalProperties: false
> +
> +allOf:
> +  - $ref: /schemas/pci/pci-bus.yaml#
> +  - $ref: /schemas/interrupt-controller/msi-controller.yaml#
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: aspeed,ast2600-pcie
> +    then:
> +      required:
> +        - aspeed,ahbc

else: make it false

> +
> +required:
> +  - interrupts
> +  - bus-range
> +  - ranges
> +  - resets
> +  - reset-names
> +  - msi-parent
> +  - msi-controller
> +  - aspeed,pciephy
> +  - aspeed,pciecfg
> +  - interrupt-map-mask
> +  - interrupt-map
> +  - interrupt-controller

Messed order, missing properties. Open other bindings...

> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/clock/ast2600-clock.h>
> +
> +    apb {
> +      #address-cells = <1>;
> +      #size-cells = <1>;
> +
> +      pcie0: pcie@1e7700C0 {
> +        compatible = "aspeed,ast2600-pcie";
> +        device_type = "pci";
> +        reg = <0x1e7700C0 0x40>;

Lower case hex. Please follow carefully DTS coding style.



Best regards,
Krzysztof

  reply	other threads:[~2025-06-13  9:50 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-13  3:29 [PATCH 0/7] Add ASPEED PCIe Root Complex support Jacky Chou
2025-06-13  3:29 ` [PATCH 1/7] dt-bindings: phy: Add document for ASPEED PCIe PHY Jacky Chou
2025-06-13  9:14   ` neil.armstrong
2025-06-20  5:03     ` 回覆: " Jacky Chou
2025-06-13  9:44   ` Krzysztof Kozlowski
2025-06-20  8:29     ` 回覆: " Jacky Chou
2025-06-13  3:29 ` [PATCH 2/7] dt-bindings: pci: Add document for ASPEED PCIe Config Jacky Chou
2025-06-13  9:46   ` Krzysztof Kozlowski
2025-06-20  8:32     ` 回覆: " Jacky Chou
2025-06-13 15:58   ` Bjorn Helgaas
2025-06-20  5:27     ` Jacky Chou
2025-06-13  3:29 ` [PATCH 3/7] dt-bindings: pci: Add document for ASPEED PCIe RC Jacky Chou
2025-06-13  9:50   ` Krzysztof Kozlowski [this message]
2025-06-20  8:36     ` Jacky Chou
2025-06-25 21:04   ` Rob Herring
2025-06-27  9:59     ` 回覆: " Jacky Chou
2025-06-13  3:29 ` [PATCH 4/7] ARM: dts: aspeed-g6: Add AST2600 PCIe RC PERST ctrl pin Jacky Chou
2025-06-13  9:51   ` Krzysztof Kozlowski
2025-06-20  8:36     ` Jacky Chou
2025-06-13 15:59   ` Bjorn Helgaas
2025-06-13  3:29 ` [PATCH 5/7] ARM: dts: aspeed-g6: Add PCIe RC node Jacky Chou
2025-06-13 15:54   ` Bjorn Helgaas
2025-06-20  5:24     ` 回覆: " Jacky Chou
2025-06-24 15:28       ` Bjorn Helgaas
2025-06-25  8:27         ` 回覆: " Jacky Chou
2025-06-25 22:16           ` Bjorn Helgaas
2025-06-27 10:02             ` Jacky Chou
2025-06-13  3:30 ` [PATCH 6/7] pinctrl: aspeed-g6: Add PCIe RC PERST pin group Jacky Chou
2025-06-18 12:15   ` Linus Walleij
2025-06-20  7:09   ` Andrew Jeffery
2025-06-13  3:30 ` [PATCH 7/7] pci: aspeed: Add ASPEED PCIe host controller driver Jacky Chou
2025-06-13  9:54   ` Krzysztof Kozlowski
2025-06-23  2:42     ` 回覆: " Jacky Chou
2025-06-13 12:03   ` Ilpo Järvinen
2025-06-23  5:41     ` Jacky Chou
2025-06-24 10:50       ` Ilpo Järvinen
2025-06-24 11:11         ` 回覆: " Jacky Chou
2025-06-24 15:40       ` Bjorn Helgaas
2025-06-25  8:32         ` 回覆: " Jacky Chou
2025-06-13 16:28   ` Bjorn Helgaas
2025-06-20  6:05     ` 回覆: " Jacky Chou
2025-06-24 15:33       ` Bjorn Helgaas
2025-06-14  2:07   ` kernel test robot
2025-06-19  8:14   ` kernel test robot
2025-06-13  9:18 ` [PATCH 0/7] Add ASPEED PCIe Root Complex support neil.armstrong
2025-06-20  8:20   ` 回覆: " Jacky Chou
2025-06-24  7:29     ` Neil Armstrong
2025-06-24 10:54       ` 回覆: " Jacky Chou
2025-06-16 21:46 ` Rob Herring (Arm)

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