From: Alexandre Courbot <acourbot@nvidia.com>
To: "Miguel Ojeda" <ojeda@kernel.org>,
"Alex Gaynor" <alex.gaynor@gmail.com>,
"Boqun Feng" <boqun.feng@gmail.com>,
"Gary Guo" <gary@garyguo.net>,
"Björn Roy Baron" <bjorn3_gh@protonmail.com>,
"Andreas Hindborg" <a.hindborg@kernel.org>,
"Alice Ryhl" <aliceryhl@google.com>,
"Trevor Gross" <tmgross@umich.edu>,
"Danilo Krummrich" <dakr@kernel.org>,
"David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>,
"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Maxime Ripard" <mripard@kernel.org>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"Benno Lossin" <lossin@kernel.org>
Cc: John Hubbard <jhubbard@nvidia.com>,
Ben Skeggs <bskeggs@nvidia.com>,
Joel Fernandes <joelagnelf@nvidia.com>,
Timur Tabi <ttabi@nvidia.com>,
Alistair Popple <apopple@nvidia.com>,
linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org,
nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
Alexandre Courbot <acourbot@nvidia.com>
Subject: [PATCH v6 12/24] gpu: nova-core: wait for GFW_BOOT completion
Date: Thu, 19 Jun 2025 22:23:56 +0900 [thread overview]
Message-ID: <20250619-nova-frts-v6-12-ecf41ef99252@nvidia.com> (raw)
In-Reply-To: <20250619-nova-frts-v6-0-ecf41ef99252@nvidia.com>
Upon reset, the GPU executes the GFW (GPU Firmware) in order to
initialize its base parameters such as clocks. The driver must ensure
that this step is completed before using the hardware.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
drivers/gpu/nova-core/gfw.rs | 41 ++++++++++++++++++++++++++++++++++++++
drivers/gpu/nova-core/gpu.rs | 5 +++++
drivers/gpu/nova-core/nova_core.rs | 1 +
drivers/gpu/nova-core/regs.rs | 25 +++++++++++++++++++++++
drivers/gpu/nova-core/util.rs | 1 -
5 files changed, 72 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/nova-core/gfw.rs b/drivers/gpu/nova-core/gfw.rs
new file mode 100644
index 0000000000000000000000000000000000000000..fa3f642bc814c7eea1ce1f2c2e24e684d1ae5fda
--- /dev/null
+++ b/drivers/gpu/nova-core/gfw.rs
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+
+//! GPU Firmware (GFW) support.
+//!
+//! Upon reset, the GPU runs some firmware code from the BIOS to setup its core parameters. Most of
+//! the GPU is considered unusable until this step is completed, so we must wait on it before
+//! performing driver initialization.
+
+use core::time::Duration;
+
+use kernel::bindings;
+use kernel::prelude::*;
+
+use crate::driver::Bar0;
+use crate::regs;
+use crate::util;
+
+/// Wait until `GFW` (GPU Firmware) completes, or a 4 seconds timeout elapses.
+pub(crate) fn wait_gfw_boot_completion(bar: &Bar0) -> Result {
+ // TIMEOUT: arbitrarily large value. GFW starts running immediately after the GPU is put out of
+ // reset, and should complete in less time than that.
+ util::wait_on(Duration::from_secs(4), || {
+ // Check that FWSEC has lowered its protection level before reading the GFW_BOOT
+ // status.
+ let gfw_booted = regs::NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK::read(bar)
+ .read_protection_level0()
+ && regs::NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT::read(bar).completed();
+
+ if gfw_booted {
+ Some(())
+ } else {
+ // Avoid busy-looping.
+ // SAFETY: msleep should be safe to call with any parameter.
+ // TODO: replace with [1] once it merges.
+ // [1] https://lore.kernel.org/rust-for-linux/20250423192857.199712-6-fujita.tomonori@gmail.com/
+ unsafe { bindings::msleep(1) };
+
+ None
+ }
+ })
+}
diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs
index 60b86f3702842dc2c8b06f092250a5bad3b97bf4..e44ff6fa07147c6dd1515c2c6c0df927a2257c85 100644
--- a/drivers/gpu/nova-core/gpu.rs
+++ b/drivers/gpu/nova-core/gpu.rs
@@ -4,6 +4,7 @@
use crate::driver::Bar0;
use crate::firmware::{Firmware, FIRMWARE_VERSION};
+use crate::gfw;
use crate::regs;
use crate::util;
use core::fmt;
@@ -182,6 +183,10 @@ pub(crate) fn new(
spec.revision
);
+ // We must wait for GFW_BOOT completion before doing any significant setup on the GPU.
+ gfw::wait_gfw_boot_completion(bar)
+ .inspect_err(|_| dev_err!(pdev.as_ref(), "GFW boot did not complete"))?;
+
Ok(pin_init!(Self {
spec,
bar: devres_bar,
diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/nova_core.rs
index 618632f0abcc8f5ef6945a04fc084acc4ecbf20b..c3fde3e132ea658888851137ab47fcb7b3637577 100644
--- a/drivers/gpu/nova-core/nova_core.rs
+++ b/drivers/gpu/nova-core/nova_core.rs
@@ -4,6 +4,7 @@
mod driver;
mod firmware;
+mod gfw;
mod gpu;
mod regs;
mod util;
diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs
index 5a12732303066f78b8ec5745096cef632ff3bfba..cba442da51181971f209b338249307c11ac481e3 100644
--- a/drivers/gpu/nova-core/regs.rs
+++ b/drivers/gpu/nova-core/regs.rs
@@ -37,3 +37,28 @@ pub(crate) fn chipset(self) -> Result<Chipset> {
.and_then(Chipset::try_from)
}
}
+
+/* PGC6 */
+
+register!(NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK @ 0x00118128 {
+ 0:0 read_protection_level0 as bool, "Set after FWSEC lowers its protection level";
+});
+
+// TODO: This is an array of registers.
+register!(NV_PGC6_AON_SECURE_SCRATCH_GROUP_05 @ 0x00118234 {
+ 31:0 value as u32;
+});
+
+register!(
+ NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT => NV_PGC6_AON_SECURE_SCRATCH_GROUP_05,
+ "Scratch group 05 register 0 used as GFW boot progress indicator" {
+ 7:0 progress as u8, "Progress of GFW boot (0xff means completed)";
+ }
+);
+
+impl NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT {
+ /// Returns `true` if GFW boot is completed.
+ pub(crate) fn completed(self) -> bool {
+ self.progress() == 0xff
+ }
+}
diff --git a/drivers/gpu/nova-core/util.rs b/drivers/gpu/nova-core/util.rs
index c50bfa5ab7fe385fae26c8909ae5984b96af618a..69f29238b25ed949b00def1b748df3ff7567d83c 100644
--- a/drivers/gpu/nova-core/util.rs
+++ b/drivers/gpu/nova-core/util.rs
@@ -34,7 +34,6 @@ pub(crate) const fn const_bytes_to_str(bytes: &[u8]) -> &str {
///
/// TODO: replace with `read_poll_timeout` once it is available.
/// (https://lore.kernel.org/lkml/20250220070611.214262-8-fujita.tomonori@gmail.com/)
-#[expect(dead_code)]
pub(crate) fn wait_on<R, F: Fn() -> Option<R>>(timeout: Duration, cond: F) -> Result<R> {
let start_time = Instant::now();
--
2.49.0
next prev parent reply other threads:[~2025-06-19 13:25 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-19 13:23 [PATCH v6 00/24] nova-core: run FWSEC-FRTS to perform first stage of GSP initialization Alexandre Courbot
2025-06-19 13:23 ` [PATCH v6 01/24] rust: dma: fix comment Alexandre Courbot
2025-06-23 15:49 ` Danilo Krummrich
2025-06-19 13:23 ` [PATCH v6 02/24] rust: dma: expose the count and size of CoherentAllocation Alexandre Courbot
2025-06-23 15:49 ` Danilo Krummrich
2025-06-19 13:23 ` [PATCH v6 03/24] rust: dma: add dma_handle_with_offset method to CoherentAllocation Alexandre Courbot
2025-06-23 15:50 ` Danilo Krummrich
2025-06-19 13:23 ` [PATCH v6 04/24] rust: make ETIMEDOUT error available Alexandre Courbot
2025-06-23 16:07 ` Miguel Ojeda
2025-06-19 13:23 ` [PATCH v6 05/24] rust: sizes: add constants up to SZ_2G Alexandre Courbot
2025-06-23 16:06 ` Miguel Ojeda
2025-06-19 13:23 ` [PATCH v6 06/24] gpu: nova-core: use absolute paths in register!() macro Alexandre Courbot
2025-06-19 13:23 ` [PATCH v6 07/24] gpu: nova-core: add delimiter for helper rules " Alexandre Courbot
2025-06-19 13:23 ` [PATCH v6 08/24] gpu: nova-core: expose the offset of each register as a type constant Alexandre Courbot
2025-06-19 13:23 ` [PATCH v6 09/24] gpu: nova-core: allow register aliases Alexandre Courbot
2025-06-19 13:23 ` [PATCH v6 10/24] gpu: nova-core: increase BAR0 size to 16MB Alexandre Courbot
2025-06-19 13:23 ` [PATCH v6 11/24] gpu: nova-core: add helper function to wait on condition Alexandre Courbot
2025-06-19 13:23 ` Alexandre Courbot [this message]
2025-06-19 13:23 ` [PATCH v6 13/24] gpu: nova-core: add DMA object struct Alexandre Courbot
2025-06-19 13:23 ` [PATCH v6 14/24] gpu: nova-core: register sysmem flush page Alexandre Courbot
2025-06-19 13:23 ` [PATCH v6 15/24] gpu: nova-core: add falcon register definitions and base code Alexandre Courbot
2025-06-19 13:24 ` [PATCH v6 16/24] gpu: nova-core: firmware: add ucode descriptor used by FWSEC-FRTS Alexandre Courbot
2025-06-19 13:24 ` [PATCH v6 17/24] gpu: nova-core: vbios: Add base support for VBIOS construction and iteration Alexandre Courbot
2025-06-19 13:24 ` [PATCH v6 18/24] gpu: nova-core: vbios: Add support to look up PMU table in FWSEC Alexandre Courbot
2025-06-19 13:24 ` [PATCH v6 19/24] gpu: nova-core: vbios: Add support for FWSEC ucode extraction Alexandre Courbot
2025-06-19 13:24 ` [PATCH v6 20/24] gpu: nova-core: compute layout of the FRTS region Alexandre Courbot
2025-06-19 13:24 ` [PATCH v6 21/24] gpu: nova-core: add types for patching firmware binaries Alexandre Courbot
2025-06-19 13:24 ` [PATCH v6 22/24] gpu: nova-core: extract FWSEC from BIOS and patch it to run FWSEC-FRTS Alexandre Courbot
2025-06-19 13:24 ` [PATCH v6 23/24] gpu: nova-core: load and " Alexandre Courbot
2025-06-19 13:24 ` [PATCH v6 24/24] gpu: nova-core: update and annotate TODO list Alexandre Courbot
2025-06-23 21:01 ` [PATCH v6 00/24] nova-core: run FWSEC-FRTS to perform first stage of GSP initialization Danilo Krummrich
2025-06-24 2:56 ` Alexandre Courbot
2025-06-24 5:17 ` John Hubbard
2025-06-30 15:43 ` Danilo Krummrich
2025-07-01 6:29 ` Alexandre Courbot
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