From: Alexandre Courbot <acourbot@nvidia.com>
To: "Miguel Ojeda" <ojeda@kernel.org>,
"Alex Gaynor" <alex.gaynor@gmail.com>,
"Boqun Feng" <boqun.feng@gmail.com>,
"Gary Guo" <gary@garyguo.net>,
"Björn Roy Baron" <bjorn3_gh@protonmail.com>,
"Andreas Hindborg" <a.hindborg@kernel.org>,
"Alice Ryhl" <aliceryhl@google.com>,
"Trevor Gross" <tmgross@umich.edu>,
"Danilo Krummrich" <dakr@kernel.org>,
"David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>,
"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Maxime Ripard" <mripard@kernel.org>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"Benno Lossin" <lossin@kernel.org>
Cc: John Hubbard <jhubbard@nvidia.com>,
Ben Skeggs <bskeggs@nvidia.com>,
Joel Fernandes <joelagnelf@nvidia.com>,
Timur Tabi <ttabi@nvidia.com>,
Alistair Popple <apopple@nvidia.com>,
linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org,
nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
Alexandre Courbot <acourbot@nvidia.com>
Subject: [PATCH v6 18/24] gpu: nova-core: vbios: Add support to look up PMU table in FWSEC
Date: Thu, 19 Jun 2025 22:24:02 +0900 [thread overview]
Message-ID: <20250619-nova-frts-v6-18-ecf41ef99252@nvidia.com> (raw)
In-Reply-To: <20250619-nova-frts-v6-0-ecf41ef99252@nvidia.com>
From: Joel Fernandes <joelagnelf@nvidia.com>
The PMU table in the FWSEC image has to be located to locate the start
of the Falcon ucode in the same or another FWSEC image. Add support for
the same.
Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
drivers/gpu/nova-core/vbios.rs | 179 ++++++++++++++++++++++++++++++++++++++++-
1 file changed, 177 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/nova-core/vbios.rs b/drivers/gpu/nova-core/vbios.rs
index b9879590ae3aae6517683a6ed02f7f639055598e..445b7ee5893c9d16a82254e70d937a902b1d0fae 100644
--- a/drivers/gpu/nova-core/vbios.rs
+++ b/drivers/gpu/nova-core/vbios.rs
@@ -330,6 +330,111 @@ fn image_size_bytes(&self) -> usize {
}
}
+/// BIOS Information Table (BIT) Header
+/// This is the head of the BIT table, that is used to locate the Falcon data.
+/// The BIT table (with its header) is in the PciAtBiosImage and the falcon data
+/// it is pointing to is in the FwSecBiosImage.
+#[derive(Debug, Clone, Copy)]
+#[expect(dead_code)]
+struct BitHeader {
+ /// 0h: BIT Header Identifier (BMP=0x7FFF/BIT=0xB8FF)
+ id: u16,
+ /// 2h: BIT Header Signature ("BIT\0")
+ signature: [u8; 4],
+ /// 6h: Binary Coded Decimal Version, ex: 0x0100 is 1.00.
+ bcd_version: u16,
+ /// 8h: Size of BIT Header (in bytes)
+ header_size: u8,
+ /// 9h: Size of BIT Tokens (in bytes)
+ token_size: u8,
+ /// 10h: Number of token entries that follow
+ token_entries: u8,
+ /// 11h: BIT Header Checksum
+ checksum: u8,
+}
+
+impl BitHeader {
+ fn new(data: &[u8]) -> Result<Self> {
+ if data.len() < 12 {
+ return Err(EINVAL);
+ }
+
+ let mut signature = [0u8; 4];
+ signature.copy_from_slice(&data[2..6]);
+
+ // Check header ID and signature
+ let id = u16::from_le_bytes([data[0], data[1]]);
+ if id != 0xB8FF || &signature != b"BIT\0" {
+ return Err(EINVAL);
+ }
+
+ Ok(BitHeader {
+ id,
+ signature,
+ bcd_version: u16::from_le_bytes([data[6], data[7]]),
+ header_size: data[8],
+ token_size: data[9],
+ token_entries: data[10],
+ checksum: data[11],
+ })
+ }
+}
+
+/// BIT Token Entry: Records in the BIT table followed by the BIT header
+#[derive(Debug, Clone, Copy)]
+#[expect(dead_code)]
+struct BitToken {
+ /// 00h: Token identifier
+ id: u8,
+ /// 01h: Version of the token data
+ data_version: u8,
+ /// 02h: Size of token data in bytes
+ data_size: u16,
+ /// 04h: Offset to the token data
+ data_offset: u16,
+}
+
+// Define the token ID for the Falcon data
+const BIT_TOKEN_ID_FALCON_DATA: u8 = 0x70;
+
+impl BitToken {
+ /// Find a BIT token entry by BIT ID in a PciAtBiosImage
+ fn from_id(image: &PciAtBiosImage, token_id: u8) -> Result<Self> {
+ let header = &image.bit_header;
+
+ // Offset to the first token entry
+ let tokens_start = image.bit_offset + header.header_size as usize;
+
+ for i in 0..header.token_entries as usize {
+ let entry_offset = tokens_start + (i * header.token_size as usize);
+
+ // Make sure we don't go out of bounds
+ if entry_offset + header.token_size as usize > image.base.data.len() {
+ return Err(EINVAL);
+ }
+
+ // Check if this token has the requested ID
+ if image.base.data[entry_offset] == token_id {
+ return Ok(BitToken {
+ id: image.base.data[entry_offset],
+ data_version: image.base.data[entry_offset + 1],
+ data_size: u16::from_le_bytes([
+ image.base.data[entry_offset + 2],
+ image.base.data[entry_offset + 3],
+ ]),
+ data_offset: u16::from_le_bytes([
+ image.base.data[entry_offset + 4],
+ image.base.data[entry_offset + 5],
+ ]),
+ });
+ }
+ }
+
+ // Token not found
+ Err(ENOENT)
+ }
+}
+
/// PCI ROM Expansion Header as defined in PCI Firmware Specification.
/// This is header is at the beginning of every image in the set of
/// images in the ROM. It contains a pointer to the PCI Data Structure
@@ -575,7 +680,8 @@ fn new(pdev: &pci::Device, data: &[u8]) -> Result<Self> {
struct PciAtBiosImage {
base: BiosImageBase,
- // PCI-AT-specific fields can be added here in the future.
+ bit_header: BitHeader,
+ bit_offset: usize,
}
struct EfiBiosImage {
@@ -599,7 +705,7 @@ impl TryFrom<BiosImageBase> for BiosImage {
fn try_from(base: BiosImageBase) -> Result<Self> {
match base.pcir.code_type {
- 0x00 => Ok(BiosImage::PciAt(PciAtBiosImage { base })),
+ 0x00 => Ok(BiosImage::PciAt(base.try_into()?)),
0x03 => Ok(BiosImage::Efi(EfiBiosImage { base })),
0x70 => Ok(BiosImage::Nbsi(NbsiBiosImage { base })),
0xE0 => Ok(BiosImage::FwSec(FwSecBiosImage { base })),
@@ -679,3 +785,72 @@ fn new(pdev: &pci::Device, data: &[u8]) -> Result<Self> {
})
}
}
+
+/// The PciAt BIOS image is typically the first BIOS image type found in the
+/// BIOS image chain. It contains the BIT header and the BIT tokens.
+impl PciAtBiosImage {
+ /// Find a byte pattern in a slice
+ fn find_byte_pattern(haystack: &[u8], needle: &[u8]) -> Result<usize> {
+ haystack
+ .windows(needle.len())
+ .position(|window| window == needle)
+ .ok_or(EINVAL)
+ }
+
+ /// Find the BIT header in the PciAtBiosImage
+ fn find_bit_header(data: &[u8]) -> Result<(BitHeader, usize)> {
+ let bit_pattern = [0xff, 0xb8, b'B', b'I', b'T', 0x00];
+ let bit_offset = Self::find_byte_pattern(data, &bit_pattern)?;
+ let bit_header = BitHeader::new(&data[bit_offset..])?;
+
+ Ok((bit_header, bit_offset))
+ }
+
+ /// Get a BIT token entry from the BIT table in the PciAtBiosImage
+ fn get_bit_token(&self, token_id: u8) -> Result<BitToken> {
+ BitToken::from_id(self, token_id)
+ }
+
+ /// Find the Falcon data pointer structure in the PciAtBiosImage
+ /// This is just a 4 byte structure that contains a pointer to the
+ /// Falcon data in the FWSEC image.
+ fn falcon_data_ptr(&self, pdev: &pci::Device) -> Result<u32> {
+ let token = self.get_bit_token(BIT_TOKEN_ID_FALCON_DATA)?;
+
+ // Make sure we don't go out of bounds
+ if token.data_offset as usize + 4 > self.base.data.len() {
+ return Err(EINVAL);
+ }
+
+ // read the 4 bytes at the offset specified in the token
+ let offset = token.data_offset as usize;
+ let bytes: [u8; 4] = self.base.data[offset..offset + 4].try_into().map_err(|_| {
+ dev_err!(pdev.as_ref(), "Failed to convert data slice to array");
+ EINVAL
+ })?;
+
+ let data_ptr = u32::from_le_bytes(bytes);
+
+ if (data_ptr as usize) < self.base.data.len() {
+ dev_err!(pdev.as_ref(), "Falcon data pointer out of bounds\n");
+ return Err(EINVAL);
+ }
+
+ Ok(data_ptr)
+ }
+}
+
+impl TryFrom<BiosImageBase> for PciAtBiosImage {
+ type Error = Error;
+
+ fn try_from(base: BiosImageBase) -> Result<Self> {
+ let data_slice = &base.data;
+ let (bit_header, bit_offset) = PciAtBiosImage::find_bit_header(data_slice)?;
+
+ Ok(PciAtBiosImage {
+ base,
+ bit_header,
+ bit_offset,
+ })
+ }
+}
--
2.49.0
next prev parent reply other threads:[~2025-06-19 13:25 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-19 13:23 [PATCH v6 00/24] nova-core: run FWSEC-FRTS to perform first stage of GSP initialization Alexandre Courbot
2025-06-19 13:23 ` [PATCH v6 01/24] rust: dma: fix comment Alexandre Courbot
2025-06-23 15:49 ` Danilo Krummrich
2025-06-19 13:23 ` [PATCH v6 02/24] rust: dma: expose the count and size of CoherentAllocation Alexandre Courbot
2025-06-23 15:49 ` Danilo Krummrich
2025-06-19 13:23 ` [PATCH v6 03/24] rust: dma: add dma_handle_with_offset method to CoherentAllocation Alexandre Courbot
2025-06-23 15:50 ` Danilo Krummrich
2025-06-19 13:23 ` [PATCH v6 04/24] rust: make ETIMEDOUT error available Alexandre Courbot
2025-06-23 16:07 ` Miguel Ojeda
2025-06-19 13:23 ` [PATCH v6 05/24] rust: sizes: add constants up to SZ_2G Alexandre Courbot
2025-06-23 16:06 ` Miguel Ojeda
2025-06-19 13:23 ` [PATCH v6 06/24] gpu: nova-core: use absolute paths in register!() macro Alexandre Courbot
2025-06-19 13:23 ` [PATCH v6 07/24] gpu: nova-core: add delimiter for helper rules " Alexandre Courbot
2025-06-19 13:23 ` [PATCH v6 08/24] gpu: nova-core: expose the offset of each register as a type constant Alexandre Courbot
2025-06-19 13:23 ` [PATCH v6 09/24] gpu: nova-core: allow register aliases Alexandre Courbot
2025-06-19 13:23 ` [PATCH v6 10/24] gpu: nova-core: increase BAR0 size to 16MB Alexandre Courbot
2025-06-19 13:23 ` [PATCH v6 11/24] gpu: nova-core: add helper function to wait on condition Alexandre Courbot
2025-06-19 13:23 ` [PATCH v6 12/24] gpu: nova-core: wait for GFW_BOOT completion Alexandre Courbot
2025-06-19 13:23 ` [PATCH v6 13/24] gpu: nova-core: add DMA object struct Alexandre Courbot
2025-06-19 13:23 ` [PATCH v6 14/24] gpu: nova-core: register sysmem flush page Alexandre Courbot
2025-06-19 13:23 ` [PATCH v6 15/24] gpu: nova-core: add falcon register definitions and base code Alexandre Courbot
2025-06-19 13:24 ` [PATCH v6 16/24] gpu: nova-core: firmware: add ucode descriptor used by FWSEC-FRTS Alexandre Courbot
2025-06-19 13:24 ` [PATCH v6 17/24] gpu: nova-core: vbios: Add base support for VBIOS construction and iteration Alexandre Courbot
2025-06-19 13:24 ` Alexandre Courbot [this message]
2025-06-19 13:24 ` [PATCH v6 19/24] gpu: nova-core: vbios: Add support for FWSEC ucode extraction Alexandre Courbot
2025-06-19 13:24 ` [PATCH v6 20/24] gpu: nova-core: compute layout of the FRTS region Alexandre Courbot
2025-06-19 13:24 ` [PATCH v6 21/24] gpu: nova-core: add types for patching firmware binaries Alexandre Courbot
2025-06-19 13:24 ` [PATCH v6 22/24] gpu: nova-core: extract FWSEC from BIOS and patch it to run FWSEC-FRTS Alexandre Courbot
2025-06-19 13:24 ` [PATCH v6 23/24] gpu: nova-core: load and " Alexandre Courbot
2025-06-19 13:24 ` [PATCH v6 24/24] gpu: nova-core: update and annotate TODO list Alexandre Courbot
2025-06-23 21:01 ` [PATCH v6 00/24] nova-core: run FWSEC-FRTS to perform first stage of GSP initialization Danilo Krummrich
2025-06-24 2:56 ` Alexandre Courbot
2025-06-24 5:17 ` John Hubbard
2025-06-30 15:43 ` Danilo Krummrich
2025-07-01 6:29 ` Alexandre Courbot
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