[PATCH v3 1/2] dt-bindings: ethernet: eswin: Document for EIC7700 SoC

[weishangjuan@eswincomputing.com]

From: Shangjuan Wei <weishangjuan@eswincomputing.com>

Add ESWIN EIC7700 Ethernet controller, supporting clock
configuration, delay adjustment and speed adaptive functions.

Signed-off-by: Zhi Li <lizhi2@eswincomputing.com>
Signed-off-by: Shangjuan Wei <weishangjuan@eswincomputing.com>
---
 .../bindings/net/eswin,eic7700-eth.yaml       | 175 ++++++++++++++++++
 1 file changed, 175 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml

diff --git a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
new file mode 100644
index 000000000000..04b4c7bfbb5b
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
@@ -0,0 +1,175 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/eswin,eic7700-eth.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Eswin EIC7700 SOC Eth Controller
+
+maintainers:
+  - Shuang Liang <liangshuang@eswincomputing.com>
+  - Zhi Li <lizhi2@eswincomputing.com>
+  - Shangjuan Wei <weishangjuan@eswincomputing.com>
+
+description:
+  The eth controller registers are part of the syscrg block on
+  the EIC7700 SoC.
+
+select:
+  properties:
+    compatible:
+      contains:
+        enum:
+          - eswin,eic7700-qos-eth
+  required:
+    - compatible
+
+allOf:
+  - $ref: snps,dwmac.yaml#
+
+properties:
+  compatible:
+    items:
+      - const: eswin,eic7700-qos-eth
+      - const: snps,dwmac-5.20
+
+  reg:
+    minItems: 1
+
+  interrupt-names:
+    const: macirq
+
+  interrupts:
+    maxItems: 1
+
+  phy-mode:
+    $ref: /schemas/types.yaml#/definitions/string
+    enum:
+      - rgmii
+      - rgmii-rxid
+      - rgmii-txid
+      - rgmii-id
+
+  phy-handle:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: Reference to the PHY device
+
+  clocks:
+    minItems: 2
+    maxItems: 2
+
+  clock-names:
+    minItems: 2
+    maxItems: 2
+    contains:
+      enum:
+        - stmmaceth
+        - tx
+
+  resets:
+    maxItems: 1
+
+  reset-names:
+    items:
+      - const: stmmaceth
+
+  rx-internal-delay-ps:
+    description:
+      RGMII Receive Clock Delay defined in pico seconds. This is used for
+      controllers that have configurable RX internal delays. If this
+      property is present then the MAC applies the RX delay.
+
+  tx-internal-delay-ps:
+    description:
+      RGMII Transmit Clock Delay defined in pico seconds. This is used for
+      controllers that have configurable TX internal delays. If this
+      property is present then the MAC applies the TX delay.
+
+  eswin,hsp-sp-csr:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      - description: Phandle to HSP(High-Speed Peripheral) device
+      - description: Control register offset
+      - description: Status register offset
+      - description: Interrupt register offset
+    description: |
+      A phandle to hsp-sp-csr with three arguments that configure
+      HSP(High-Speed Peripheral) device. The argument one is the
+      offset of control register, the argument two is the offset
+      of status register, the argument three is the offset of
+      interrupt register.
+
+  eswin,syscrg-csr:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      - description:
+          Phandle to system CRG(System Clock and Reset Generator)
+          device
+      - description: Clock control register offset
+      - description: Reset control register offset
+    description: |
+      A phandle to syscrg-csr with two arguments that configure
+      CRG(System Clock and Reset Generator) device. The argument
+      one is the offset of clock control register, the argument
+      two is the offset of reset control register.
+
+  eswin,dly-hsp-reg:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    items:
+      - description: Control the delay of TXD
+      - description: Control the CLK delay of TX and RX
+      - description: Control the delay of RXD
+    description: |
+      An array to dly-hsp-reg with three arguments that
+      configure delay. The argument one is used to control the
+      delay of TXD, the argument two is used to control the
+      CLK delay of TX and RX, the argument three is used to
+      control the delay of RXD.
+
+required:
+  - compatible
+  - reg
+  - interrupt-names
+  - interrupts
+  - phy-mode
+  - rx-internal-delay-ps
+  - tx-internal-delay-ps
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - eswin,hsp-sp-csr
+  - eswin,syscrg-csr
+  - eswin,dly-hsp-reg
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    ethernet@50400000 {
+        compatible = "eswin,eic7700-qos-eth", "snps,dwmac-5.20";
+        reg = <0x50400000 0x10000>;
+        interrupt-parent = <&plic>;
+        interrupt-names = "macirq";
+        interrupts = <61>;
+        phy-mode = "rgmii";
+        phy-handle = <&phy0>;
+        rx-internal-delay-ps = <9000>;
+        tx-internal-delay-ps = <2200>;
+        clocks = <&clock 417>, <&clock 418>;
+        clock-names = "stmmaceth", "tx";
+        resets = <&reset 95>;
+        reset-names = "stmmaceth";
+        eswin,hsp-sp-csr = <&hsp_sp_csr 0x1030 0x100 0x108>;
+        eswin,syscrg-csr = <&sys_crg 0x148 0x14c>;
+        eswin,dly-hsp-reg = <0x114 0x118 0x11c>;
+        snps,axi-config = <&stmmac_axi_setup>;
+        snps,fixed-burst;
+        snps,aal;
+        snps,tso;
+        stmmac_axi_setup: stmmac-axi-config {
+            snps,blen = <0 0 0 0 16 8 4>;
+            snps,rd_osr_lmt = <2>;
+            snps,wr_osr_lmt = <2>;
+        };
+    };
--
2.17.1