From: James Morse <james.morse@arm.com>
To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Cc: Rob Herring <robh@kernel.org>, Ben Horgan <ben.horgan@arm.com>,
Rohit Mathew <rohit.mathew@arm.com>,
Shanker Donthineni <sdonthineni@nvidia.com>,
Zeng Heng <zengheng4@huawei.com>,
Lecopzer Chen <lecopzerc@nvidia.com>,
Carl Worth <carl@os.amperecomputing.com>,
shameerali.kolothum.thodi@huawei.com,
D Scott Phillips OS <scott@os.amperecomputing.com>,
lcherian@marvell.com, bobo.shaobowang@huawei.com,
tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com,
Jamie Iles <quic_jiles@quicinc.com>,
Xin Hao <xhao@linux.alibaba.com>,
peternewman@google.com, dfustini@baylibre.com,
amitsinght@marvell.com, David Hildenbrand <david@redhat.com>,
Rex Nie <rex.nie@jaguarmicro.com>,
Dave Martin <dave.martin@arm.com>, Koba Ko <kobak@nvidia.com>,
James Morse <james.morse@arm.com>
Subject: [RFC PATCH 18/36] arm_mpam: Probe MSCs to find the supported partid/pmg values
Date: Fri, 11 Jul 2025 18:36:30 +0000 [thread overview]
Message-ID: <20250711183648.30766-19-james.morse@arm.com> (raw)
In-Reply-To: <20250711183648.30766-1-james.morse@arm.com>
CPUs can generate traffic with a range of PARTID and PMG values,
but each MSC may have its own maximum size for these fields.
Before MPAM can be used, the driver needs to probe each RIS on
each MSC, to find the system-wide smallest value that can be used.
While doing this, RIS entries that firmware didn't describe are create
under MPAM_CLASS_UNKNOWN.
While we're here, implement the mpam_register_requestor() call
for the arch code. Future callers of this will tell us about the
SMMU and ITS.
Signed-off-by: James Morse <james.morse@arm.com>
---
drivers/platform/arm64/mpam/mpam_devices.c | 172 +++++++++++++++++++-
drivers/platform/arm64/mpam/mpam_internal.h | 6 +
include/linux/arm_mpam.h | 14 ++
3 files changed, 185 insertions(+), 7 deletions(-)
diff --git a/drivers/platform/arm64/mpam/mpam_devices.c b/drivers/platform/arm64/mpam/mpam_devices.c
index 89434ae3efa6..8646fb85ad09 100644
--- a/drivers/platform/arm64/mpam/mpam_devices.c
+++ b/drivers/platform/arm64/mpam/mpam_devices.c
@@ -6,6 +6,7 @@
#include <linux/acpi.h>
#include <linux/atomic.h>
#include <linux/arm_mpam.h>
+#include <linux/bitfield.h>
#include <linux/cacheinfo.h>
#include <linux/cpu.h>
#include <linux/cpumask.h>
@@ -44,6 +45,15 @@ static u32 mpam_num_msc;
static int mpam_cpuhp_state;
static DEFINE_MUTEX(mpam_cpuhp_state_lock);
+/*
+ * The smallest common values for any CPU or MSC in the system.
+ * Generating traffic outside this range will result in screaming interrupts.
+ */
+u16 mpam_partid_max;
+u8 mpam_pmg_max;
+static bool partid_max_init, partid_max_published;
+static DEFINE_SPINLOCK(partid_max_lock);
+
/*
* mpam is enabled once all devices have been probed from CPU online callbacks,
* scheduled via this work_struct. If access to an MSC depends on a CPU that
@@ -106,6 +116,74 @@ static inline u32 _mpam_read_partsel_reg(struct mpam_msc *msc, u16 reg)
#define mpam_read_partsel_reg(msc, reg) _mpam_read_partsel_reg(msc, MPAMF_##reg)
+static void __mpam_write_reg(struct mpam_msc *msc, u16 reg, u32 val)
+{
+ WARN_ON_ONCE(reg + sizeof(u32) > msc->mapped_hwpage_sz);
+ WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), &msc->accessibility));
+
+ writel_relaxed(val, msc->mapped_hwpage + reg);
+}
+
+static inline void _mpam_write_partsel_reg(struct mpam_msc *msc, u16 reg, u32 val)
+{
+ lockdep_assert_held_once(&msc->part_sel_lock);
+ __mpam_write_reg(msc, reg, val);
+}
+#define mpam_write_partsel_reg(msc, reg, val) _mpam_write_partsel_reg(msc, MPAMCFG_##reg, val)
+
+static u64 mpam_msc_read_idr(struct mpam_msc *msc)
+{
+ u64 idr_high = 0, idr_low;
+
+ lockdep_assert_held(&msc->part_sel_lock);
+
+ idr_low = mpam_read_partsel_reg(msc, IDR);
+ if (FIELD_GET(MPAMF_IDR_HAS_EXT, idr_low))
+ idr_high = mpam_read_partsel_reg(msc, IDR + 4);
+
+ return (idr_high << 32) | idr_low;
+}
+
+static void __mpam_part_sel_raw(u32 partsel, struct mpam_msc *msc)
+{
+ lockdep_assert_held(&msc->part_sel_lock);
+
+ mpam_write_partsel_reg(msc, PART_SEL, partsel);
+}
+
+static void __mpam_part_sel(u8 ris_idx, u16 partid, struct mpam_msc *msc)
+{
+ u32 partsel = FIELD_PREP(MPAMCFG_PART_SEL_RIS, ris_idx) |
+ FIELD_PREP(MPAMCFG_PART_SEL_PARTID_SEL, partid);
+
+ __mpam_part_sel_raw(partsel, msc);
+}
+
+int mpam_register_requestor(u16 partid_max, u8 pmg_max)
+{
+ int err = 0;
+
+ lockdep_assert_irqs_enabled();
+
+ spin_lock(&partid_max_lock);
+ if (!partid_max_init) {
+ mpam_partid_max = partid_max;
+ mpam_pmg_max = pmg_max;
+ partid_max_init = true;
+ } else if (!partid_max_published) {
+ mpam_partid_max = min(mpam_partid_max, partid_max);
+ mpam_pmg_max = min(mpam_pmg_max, pmg_max);
+ } else {
+ /* New requestors can't lower the values */
+ if (partid_max < mpam_partid_max || pmg_max < mpam_pmg_max)
+ err = -EBUSY;
+ }
+ spin_unlock(&partid_max_lock);
+
+ return err;
+}
+EXPORT_SYMBOL(mpam_register_requestor);
+
#define init_garbage(x) init_llist_node(&(x)->garbage.llist)
static struct mpam_vmsc *
@@ -522,6 +600,7 @@ static int mpam_ris_create_locked(struct mpam_msc *msc, u8 ris_idx,
cpumask_or(&comp->affinity, &comp->affinity, &ris->affinity);
cpumask_or(&class->affinity, &class->affinity, &ris->affinity);
list_add_rcu(&ris->vmsc_list, &vmsc->ris);
+ list_add_rcu(&ris->msc_list, &msc->ris);
return 0;
}
@@ -541,10 +620,37 @@ int mpam_ris_create(struct mpam_msc *msc, u8 ris_idx,
return err;
}
+static struct mpam_msc_ris *mpam_get_or_create_ris(struct mpam_msc *msc,
+ u8 ris_idx)
+{
+ int err;
+ struct mpam_msc_ris *ris, *found = ERR_PTR(-ENOENT);
+
+ lockdep_assert_held(&mpam_list_lock);
+
+ if (!test_bit(ris_idx, msc->ris_idxs)) {
+ err = mpam_ris_create_locked(msc, ris_idx, MPAM_CLASS_UNKNOWN,
+ 0, 0, GFP_ATOMIC);
+ if (err)
+ return ERR_PTR(err);
+ }
+
+ list_for_each_entry(ris, &msc->ris, msc_list) {
+ if (ris->ris_idx == ris_idx) {
+ found = ris;
+ break;
+ }
+ }
+
+ return found;
+}
+
static int mpam_msc_hw_probe(struct mpam_msc *msc)
{
u64 idr;
- int err;
+ u16 partid_max;
+ u8 ris_idx, pmg_max;
+ struct mpam_msc_ris *ris;
lockdep_assert_held(&msc->probe_lock);
@@ -553,14 +659,42 @@ static int mpam_msc_hw_probe(struct mpam_msc *msc)
if ((idr & MPAMF_AIDR_ARCH_MAJOR_REV) != MPAM_ARCHITECTURE_V1) {
pr_err_once("%s does not match MPAM architecture v1.0\n",
dev_name(&msc->pdev->dev));
- err = -EIO;
- } else {
- msc->probed = true;
- err = 0;
+ mutex_unlock(&msc->part_sel_lock);
+ return -EIO;
}
+
+ idr = mpam_msc_read_idr(msc);
mutex_unlock(&msc->part_sel_lock);
+ msc->ris_max = FIELD_GET(MPAMF_IDR_RIS_MAX, idr);
- return err;
+ /* Use these values so partid/pmg always starts with a valid value */
+ msc->partid_max = FIELD_GET(MPAMF_IDR_PARTID_MAX, idr);
+ msc->pmg_max = FIELD_GET(MPAMF_IDR_PMG_MAX, idr);
+
+ for (ris_idx = 0; ris_idx <= msc->ris_max; ris_idx++) {
+ mutex_lock(&msc->part_sel_lock);
+ __mpam_part_sel(ris_idx, 0, msc);
+ idr = mpam_msc_read_idr(msc);
+ mutex_unlock(&msc->part_sel_lock);
+
+ partid_max = FIELD_GET(MPAMF_IDR_PARTID_MAX, idr);
+ pmg_max = FIELD_GET(MPAMF_IDR_PMG_MAX, idr);
+ msc->partid_max = min(msc->partid_max, partid_max);
+ msc->pmg_max = min(msc->pmg_max, pmg_max);
+
+ ris = mpam_get_or_create_ris(msc, ris_idx);
+ if (IS_ERR(ris))
+ return PTR_ERR(ris);
+ }
+
+ spin_lock(&partid_max_lock);
+ mpam_partid_max = min(mpam_partid_max, msc->partid_max);
+ mpam_pmg_max = min(mpam_pmg_max, msc->pmg_max);
+ spin_unlock(&partid_max_lock);
+
+ msc->probed = true;
+
+ return 0;
}
static int mpam_cpu_online(unsigned int cpu)
@@ -907,9 +1041,18 @@ static void mpam_enable_once(void)
mpam_cpuhp_state = 0;
mutex_unlock(&mpam_cpuhp_state_lock);
+ /*
+ * Once the cpuhp callbacks have been changed, mpam_partid_max can no
+ * longer change.
+ */
+ spin_lock(&partid_max_lock);
+ partid_max_published = true;
+ spin_unlock(&partid_max_lock);
+
mpam_register_cpuhp_callbacks(mpam_cpu_online, mpam_cpu_offline);
- pr_info("MPAM enabled\n");
+ printk(KERN_INFO "MPAM enabled with %u partid and %u pmg\n",
+ mpam_partid_max + 1, mpam_pmg_max + 1);
}
/*
@@ -959,11 +1102,25 @@ static void mpam_dt_create_foundling_msc(void)
static int __init mpam_msc_driver_init(void)
{
+ bool mpam_not_available = false;
+
if (!system_supports_mpam())
return -EOPNOTSUPP;
init_srcu_struct(&mpam_srcu);
+ /*
+ * If the MPAM CPU interface is not implemented, or reserved by
+ * firmware, there is no point touching the rest of the hardware.
+ */
+ spin_lock(&partid_max_lock);
+ if (!partid_max_init || (!mpam_partid_max && !mpam_pmg_max))
+ mpam_not_available = true;
+ spin_unlock(&partid_max_lock);
+
+ if (mpam_not_available)
+ return 0;
+
if (!acpi_disabled)
fw_num_msc = acpi_mpam_count_msc();
else
@@ -979,4 +1136,5 @@ static int __init mpam_msc_driver_init(void)
return platform_driver_register(&mpam_msc_driver);
}
+/* Must occur after arm64_mpam_register_cpus() from arch_initcall() */
subsys_initcall(mpam_msc_driver_init);
diff --git a/drivers/platform/arm64/mpam/mpam_internal.h b/drivers/platform/arm64/mpam/mpam_internal.h
index f56e69ff8397..eb5cc6775d54 100644
--- a/drivers/platform/arm64/mpam/mpam_internal.h
+++ b/drivers/platform/arm64/mpam/mpam_internal.h
@@ -50,6 +50,8 @@ struct mpam_msc {
*/
struct mutex probe_lock;
bool probed;
+ u16 partid_max;
+ u8 pmg_max;
unsigned long ris_idxs[128 / BITS_PER_LONG];
u32 ris_max;
@@ -148,6 +150,10 @@ struct mpam_msc_ris {
extern struct srcu_struct mpam_srcu;
extern struct list_head mpam_classes;
+/* System wide partid/pmg values */
+extern u16 mpam_partid_max;
+extern u8 mpam_pmg_max;
+
/* Scheduled work callback to enable mpam once all MSC have been probed */
void mpam_enable(struct work_struct *work);
diff --git a/include/linux/arm_mpam.h b/include/linux/arm_mpam.h
index 406a77be68cb..8af93794c7a2 100644
--- a/include/linux/arm_mpam.h
+++ b/include/linux/arm_mpam.h
@@ -39,4 +39,18 @@ static inline int acpi_mpam_count_msc(void) { return -EINVAL; }
int mpam_ris_create(struct mpam_msc *msc, u8 ris_idx,
enum mpam_class_types type, u8 class_id, int component_id);
+/**
+ * mpam_register_requestor() - Register a requestor with the MPAM driver
+ * @partid_max: The maximum PARTID value the requestor can generate.
+ * @pmg_max: The maximum PMG value the requestor can generate.
+ *
+ * Registers a requestor with the MPAM driver to ensure the chosen system-wide
+ * minimum PARTID and PMG values will allow the requestors features to be used.
+ *
+ * Returns an error if the registration is too late, and a larger PARTID/PMG
+ * value has been advertised to user-space. In this case the requestor should
+ * not use its MPAM features. Returns 0 on success.
+ */
+int mpam_register_requestor(u16 partid_max, u8 pmg_max);
+
#endif /* __LINUX_ARM_MPAM_H */
--
2.39.5
next prev parent reply other threads:[~2025-07-11 18:38 UTC|newest]
Thread overview: 117+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-11 18:36 [RFC PATCH 00/36] arm_mpam: Add basic mpam driver James Morse
2025-07-11 18:36 ` [RFC PATCH 01/36] cacheinfo: Set cache 'id' based on DT data James Morse
2025-07-11 18:36 ` [RFC PATCH 02/36] cacheinfo: Add arch hook to compress CPU h/w id into 32 bits for cache-id James Morse
2025-07-11 18:36 ` [RFC PATCH 03/36] arm64: cacheinfo: Provide helper to compress MPIDR value into u32 James Morse
2025-07-11 18:36 ` [RFC PATCH 04/36] cacheinfo: Expose the code to generate a cache-id from a device_node James Morse
2025-07-14 11:40 ` Ben Horgan
2025-07-25 17:08 ` James Morse
2025-07-28 8:37 ` Ben Horgan
2025-07-11 18:36 ` [RFC PATCH 05/36] ACPI / PPTT: Add a helper to fill a cpumask from a processor container James Morse
2025-07-17 7:58 ` Shaopeng Tan (Fujitsu)
2025-07-25 17:06 ` James Morse
2025-07-22 14:28 ` Jonathan Cameron
2025-07-25 17:05 ` James Morse
2025-07-23 14:42 ` Ben Horgan
2025-07-25 17:05 ` James Morse
2025-07-11 18:36 ` [RFC PATCH 06/36] ACPI / PPTT: Stop acpi_count_levels() expecting callers to clear levels James Morse
2025-07-16 15:51 ` Jonathan Cameron
2025-07-25 17:05 ` James Morse
2025-07-11 18:36 ` [RFC PATCH 07/36] ACPI / PPTT: Find cache level by cache-id James Morse
2025-07-14 11:42 ` Ben Horgan
2025-08-05 17:06 ` James Morse
2025-07-16 16:21 ` [RFC PATCH 07/36] ACPI / PPTT: Find cache level by cache-idUIRE Jonathan Cameron
2025-08-05 17:06 ` [RFC PATCH 07/36] ACPI / PPTT: Find cache level by cache-id James Morse
2025-07-11 18:36 ` [RFC PATCH 08/36] ACPI / PPTT: Add a helper to fill a cpumask from a cache_id James Morse
2025-07-16 16:24 ` Jonathan Cameron
2025-08-05 17:06 ` James Morse
2025-07-11 18:36 ` [RFC PATCH 09/36] arm64: kconfig: Add Kconfig entry for MPAM James Morse
2025-07-16 16:26 ` Jonathan Cameron
2025-07-11 18:36 ` [RFC PATCH 10/36] ACPI / MPAM: Parse the MPAM table James Morse
2025-07-16 17:07 ` Jonathan Cameron
2025-07-23 16:39 ` Ben Horgan
2025-08-05 17:07 ` James Morse
2025-08-15 9:33 ` Ben Horgan
2025-07-28 10:08 ` Jonathan Cameron
2025-08-05 17:08 ` James Morse
2025-08-05 17:07 ` James Morse
2025-07-24 10:50 ` Ben Horgan
2025-08-05 17:08 ` James Morse
2025-07-11 18:36 ` [RFC PATCH 11/36] dt-bindings: arm: Add MPAM MSC binding James Morse
2025-07-11 21:43 ` Rob Herring
2025-08-05 17:08 ` James Morse
2025-07-11 18:36 ` [RFC PATCH 12/36] platform: arm64: Move ec devices to an ec subdirectory James Morse
2025-07-21 16:32 ` Jonathan Cameron
2025-08-06 18:03 ` James Morse
2025-07-24 10:56 ` Ben Horgan
2025-08-06 18:03 ` James Morse
2025-07-11 18:36 ` [RFC PATCH 13/36] arm_mpam: Add probe/remove for mpam msc driver and kbuild boiler plate James Morse
2025-07-24 11:02 ` Ben Horgan
2025-08-06 18:03 ` James Morse
2025-07-24 12:09 ` Catalin Marinas
2025-08-06 18:04 ` James Morse
2025-08-07 17:50 ` Drew Fustini
2025-07-11 18:36 ` [RFC PATCH 14/36] arm_mpam: Add support for memory controller MSC on DT platforms James Morse
2025-07-11 18:36 ` [RFC PATCH 15/36] arm_mpam: Add the class and component structures for ris firmware described James Morse
2025-07-11 18:36 ` [RFC PATCH 16/36] arm_mpam: Add MPAM MSC register layout definitions James Morse
2025-07-17 1:04 ` Shaopeng Tan (Fujitsu)
2025-08-06 18:04 ` James Morse
2025-07-24 14:02 ` Ben Horgan
2025-08-06 18:05 ` James Morse
2025-07-11 18:36 ` [RFC PATCH 17/36] arm_mpam: Add cpuhp callbacks to probe MSC hardware James Morse
2025-07-24 14:13 ` Ben Horgan
2025-08-06 18:07 ` James Morse
2025-07-29 6:11 ` Baisheng Gao
2025-08-06 18:07 ` James Morse
2025-08-05 8:46 ` Jonathan Cameron
2025-07-11 18:36 ` James Morse [this message]
2025-07-11 18:36 ` [RFC PATCH 19/36] arm_mpam: Add helpers for managing the locking around the mon_sel registers James Morse
2025-07-11 18:36 ` [RFC PATCH 20/36] arm_mpam: Probe the hardware features resctrl supports James Morse
2025-07-24 15:08 ` Ben Horgan
2025-07-28 16:16 ` Jonathan Cameron
2025-08-07 18:26 ` James Morse
2025-07-28 8:56 ` Ben Horgan
2025-08-08 7:20 ` James Morse
2025-07-11 18:36 ` [RFC PATCH 21/36] arm_mpam: Merge supported features during mpam_enable() into mpam_class James Morse
2025-07-28 9:15 ` Ben Horgan
2025-07-11 18:36 ` [RFC PATCH 22/36] arm_mpam: Reset MSC controls from cpu hp callbacks James Morse
2025-07-28 9:49 ` Ben Horgan
2025-08-08 7:05 ` James Morse
2025-07-11 18:36 ` [RFC PATCH 23/36] arm_mpam: Add a helper to touch an MSC from any CPU James Morse
2025-07-11 18:36 ` [RFC PATCH 24/36] arm_mpam: Extend reset logic to allow devices to be reset any time James Morse
2025-07-28 10:22 ` Ben Horgan
2025-08-08 7:07 ` James Morse
2025-07-11 18:36 ` [RFC PATCH 25/36] arm_mpam: Register and enable IRQs James Morse
2025-07-16 7:31 ` Shaopeng Tan (Fujitsu)
2025-08-08 7:08 ` James Morse
2025-07-17 1:08 ` Shaopeng Tan (Fujitsu)
2025-08-08 7:07 ` James Morse
2025-07-22 15:06 ` Jonathan Cameron
2025-08-08 7:11 ` James Morse
2025-07-28 10:49 ` Ben Horgan
2025-08-08 7:11 ` James Morse
2025-08-04 16:53 ` Fenghua Yu
2025-08-08 7:12 ` James Morse
2025-07-11 18:36 ` [RFC PATCH 26/36] arm_mpam: Use a static key to indicate when mpam is enabled James Morse
2025-07-11 18:36 ` [RFC PATCH 27/36] arm_mpam: Allow configuration to be applied and restored during cpu online James Morse
2025-07-16 6:49 ` Shaopeng Tan (Fujitsu)
2025-08-08 7:13 ` James Morse
2025-07-28 11:59 ` Ben Horgan
2025-07-28 15:34 ` Dave Martin
2025-08-08 7:16 ` James Morse
2025-08-08 7:14 ` James Morse
2025-08-04 16:39 ` Fenghua Yu
2025-08-08 7:17 ` James Morse
2025-07-11 18:36 ` [RFC PATCH 28/36] arm_mpam: Probe and reset the rest of the features James Morse
2025-07-11 18:36 ` [RFC PATCH 29/36] arm_mpam: Add helpers to allocate monitors James Morse
2025-07-11 18:36 ` [RFC PATCH 30/36] arm_mpam: Add mpam_msmon_read() to read monitor value James Morse
2025-07-28 13:02 ` Ben Horgan
2025-07-11 18:36 ` [RFC PATCH 31/36] arm_mpam: Track bandwidth counter state for overflow and power management James Morse
2025-07-11 18:36 ` [RFC PATCH 32/36] arm_mpam: Probe for long/lwd mbwu counters James Morse
2025-07-11 18:36 ` [RFC PATCH 33/36] arm_mpam: Use long MBWU counters if supported James Morse
2025-07-28 13:46 ` Ben Horgan
2025-08-08 7:19 ` James Morse
2025-07-11 18:36 ` [RFC PATCH 34/36] arm_mpam: Add helper to reset saved mbwu state James Morse
2025-07-11 18:36 ` [RFC PATCH 35/36] arm_mpam: Add kunit test for bitmap reset James Morse
2025-07-11 18:36 ` [RFC PATCH 36/36] arm_mpam: Add kunit tests for props_mismatch() James Morse
2025-08-01 16:09 ` [RFC PATCH 00/36] arm_mpam: Add basic mpam driver Jonathan Cameron
2025-08-08 7:23 ` James Morse
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