From: Rama devi Veggalam <rama.devi.veggalam@amd.com>
To: <bp@alien8.de>, <tony.luck@intel.com>, <michal.simek@amd.com>,
<robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>
Cc: <linux-kernel@vger.kernel.org>, <linux-edac@vger.kernel.org>,
<devicetree@vger.kernel.org>, <james.morse@arm.com>,
<mchehab@kernel.org>, <rric@kernel.org>, <git@amd.com>,
Rama devi Veggalam <rama.devi.veggalam@amd.com>
Subject: [PATCH v2 1/4] dt-bindings: edac: Add bindings for Xilinx Versal EDAC for XilSem
Date: Tue, 22 Jul 2025 21:33:12 +0530 [thread overview]
Message-ID: <20250722160315.2979294-2-rama.devi.veggalam@amd.com> (raw)
In-Reply-To: <20250722160315.2979294-1-rama.devi.veggalam@amd.com>
Add device tree bindings for Xilinx Versal EDAC for
XilSem controller
Signed-off-by: Rama devi Veggalam <rama.devi.veggalam@amd.com>
---
Changes in v2:
- Changed "xlnx,versal-xilsem-edac" to constant
- Removed "compatible: in required section
- Removed "|" in description
- Removed "items" in compatible
- Fixed indentation in examples
- Updated title and description
---
.../edac/xlnx,versal-xilsem-edac.yaml | 42 +++++++++++++++++++
1 file changed, 42 insertions(+)
create mode 100644 Documentation/devicetree/bindings/edac/xlnx,versal-xilsem-edac.yaml
diff --git a/Documentation/devicetree/bindings/edac/xlnx,versal-xilsem-edac.yaml b/Documentation/devicetree/bindings/edac/xlnx,versal-xilsem-edac.yaml
new file mode 100644
index 000000000000..23c1d0557a66
--- /dev/null
+++ b/Documentation/devicetree/bindings/edac/xlnx,versal-xilsem-edac.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/edac/xlnx,versal-xilsem-edac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Versal Soft Error Mitigation (XilSEM) EDAC
+
+maintainers:
+ - Rama Devi Veggalam <rama.devi.veggalam@amd.com>
+
+description:
+ Xilinx Versal Soft Error Mitigation (XilSEM) is part of the
+ Platform Loader and Manager (PLM) which is loaded into and runs on the
+ Platform Management Controller (PMC). XilSEM is responsible for reporting
+ and optionally correcting soft errors in Configuration Memory of Versal.
+ The memory is scanned by a hardware controller in the Versal Programmable
+ Logic (PL). During the scan, if the controller detects any error, be it
+ correctable or uncorrectable, it reports the error to PLM. The XilSEM on PLM
+ performs the error validation and notifies the errors to user application.
+ This XilSEM EDAC node is responsible for handling error events received from
+ XilSEM on PLM and also provides an interface to control scan operations and
+ fetching the scan status & configuration information.
+
+properties:
+ compatible:
+ const: xlnx,versal-xilsem-edac
+
+ reg:
+ maxItems: 1
+
+required:
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ edac@f2014050 {
+ compatible = "xlnx,versal-xilsem-edac";
+ reg = <0xf2014050 0xc4>;
+ };
--
2.23.0
next prev parent reply other threads:[~2025-07-22 16:03 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-22 16:03 [PATCH v2 0/4] Add support for Versal Xilsem edac Rama devi Veggalam
2025-07-22 16:03 ` Rama devi Veggalam [this message]
2025-07-23 8:05 ` [PATCH v2 1/4] dt-bindings: edac: Add bindings for Xilinx Versal EDAC for XilSem Krzysztof Kozlowski
2025-07-22 16:03 ` [PATCH v2 2/4] Documentation: ABI: Add ABI doc for xilsem edac sysfs Rama devi Veggalam
2025-07-22 16:03 ` [PATCH v2 3/4] firmware: xilinx: Add support for Xilsem scan operations Rama devi Veggalam
2025-07-22 16:03 ` [PATCH v2 4/4] edac: xilinx: Add EDAC support for Xilinx XilSem Rama devi Veggalam
2025-07-22 16:49 ` [PATCH v2 0/4] Add support for Versal Xilsem edac Borislav Petkov
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