Re: [PATCH v2 6/8] arm64: dts: bst: add support for Black Sesame Technologies C1200 CDCU1.0 board and defconfig

[Albert Yang <yangzh0906@thundersoft.com>]

On Wed, Jul 02, 2025 at 01:15:13PM +0100, Robin Murphy wrote:
> On 2025-07-02 10:44 am, Albert Yang wrote:
> > +   timer {
> > +           compatible = "arm,armv8-timer";
> > +           interrupt-parent = <&gic>;
> > +           always-on;
> > +           interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> > +                        <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> > +                        <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> > +                        <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
>
> Your PPIs target 8 of the 4 CPUS? Either way you don't have GICv2, please
> use the GICv3 binding.

 Thank you for pointing out the issue. The mask has been removed according to the GIC v3 
 format.

>
> > +           mmc0: mmc@22200000 {
> > +                   compatible = "bst,c1200-dwcmshc-sdhci";
> > +                   reg = <0x0 0x22200000 0x0 0x1000>,
> > +                         <0x0 0x23006000 0x0 0x1000>;
> > +                   interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
> > +                   clocks = <&clk_mmc>;
> > +                   clock-names = "core";
> > +                   max-frequency = <200000000>;
> > +                   bus-width = <8>;
> > +                   non-removable;
> > +                   dma-coherent;
>
> Given the funky DMA setup, I can't help be mildly suspicious of this - is
> the device genuinely I/O coherent and capable of snooping the CPU caches, or
> are you only getting away with it because dma_init_coherent_memory() happens
> to remap as non-cacheable regardless?

We allocated a portion of SRAM to serve as a bounce buffer. This buffer is incorporated 
into the system's CMA (Contiguous Memory Allocator) framework through a shared DMA mechanism
and requires memory coherency.

Best Regards,
Albert