From: Chenghai Huang <huangchenghai2@huawei.com>
To: <herbert@gondor.apana.org.au>, <davem@davemloft.net>
Cc: <linux-kernel@vger.kernel.org>, <linux-crypto@vger.kernel.org>,
<liulongfang@huawei.com>, <shenyang39@huawei.com>,
<qianweili@huawei.com>, <linwenkai6@hisilicon.com>,
<wangzhou1@hisilicon.com>, <huangchenghai2@huawei.com>
Subject: [PATCH 6/6] crypto: hisilicon/zip - enable literal length in stream mode compression
Date: Sat, 16 Aug 2025 18:28:34 +0800 [thread overview]
Message-ID: <20250816102834.828655-7-huangchenghai2@huawei.com> (raw)
In-Reply-To: <20250816102834.828655-1-huangchenghai2@huawei.com>
In stream mode, the hardware needs to combine the length of the
previous literal to calculate the length of the current literal.
Signed-off-by: Chenghai Huang <huangchenghai2@huawei.com>
---
drivers/crypto/hisilicon/zip/zip_main.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/crypto/hisilicon/zip/zip_main.c b/drivers/crypto/hisilicon/zip/zip_main.c
index 7d55cd08cd1e..c75db858bb76 100644
--- a/drivers/crypto/hisilicon/zip/zip_main.c
+++ b/drivers/crypto/hisilicon/zip/zip_main.c
@@ -117,6 +117,9 @@
/* zip comp high performance */
#define HZIP_HIGH_PERF_OFFSET 0x301208
+#define HZIP_LIT_LEN_EN_OFFSET 0x301204
+#define HZIP_LIT_LEN_EN_EN BIT(4)
+
enum {
HZIP_HIGH_COMP_RATE,
HZIP_HIGH_COMP_PERF,
@@ -454,6 +457,20 @@ bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg)
return false;
}
+static void hisi_zip_literal_set(struct hisi_qm *qm)
+{
+ u32 val;
+
+ if (qm->ver < QM_HW_V3)
+ return;
+
+ val = readl_relaxed(qm->io_base + HZIP_LIT_LEN_EN_OFFSET);
+ val &= ~HZIP_LIT_LEN_EN_EN;
+
+ /* enable literal length in stream mode compression */
+ writel(val, qm->io_base + HZIP_LIT_LEN_EN_OFFSET);
+}
+
static void hisi_zip_set_high_perf(struct hisi_qm *qm)
{
u32 val;
@@ -616,6 +633,8 @@ static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm)
CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) |
FIELD_PREP(CQC_CACHE_WB_THRD, 1), base + QM_CACHE_CTL);
+ hisi_zip_literal_set(qm);
+
hisi_zip_set_high_perf(qm);
hisi_zip_enable_clock_gate(qm);
--
2.33.0
prev parent reply other threads:[~2025-08-16 10:28 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-16 10:28 [PATCH 0/6] crypto: hisilicon - enhancements and fixes for device reset and configuration Chenghai Huang
2025-08-16 10:28 ` [PATCH 1/6] crypto: hisilicon - re-enable address prefetch after device resuming Chenghai Huang
2025-08-20 7:01 ` Weili Qian
2025-08-16 10:28 ` [PATCH 2/6] crypto: hisilicon/zip - remove unnecessary validation for high-performance mode configurations Chenghai Huang
2025-08-16 10:28 ` [PATCH 3/6] crypto: hisilicon - check the sva module status while enabling or disabling address prefetch Chenghai Huang
2025-08-16 10:28 ` [PATCH 4/6] crypto: hisilicon/qm - check whether the input function and PF are on the same device Chenghai Huang
2025-08-16 10:28 ` [PATCH 5/6] crypto: hisilicon/qm - request reserved interrupt for virtual function Chenghai Huang
2025-08-16 10:28 ` Chenghai Huang [this message]
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