From: fangyu.yu@linux.alibaba.com
To: anup@brainfault.org, atish.patra@linux.dev,
paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr
Cc: guoren@linux.alibaba.com, guoren@kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org,
Fangyu Yu <fangyu.yu@linux.alibaba.com>
Subject: [PATCH V2] RISC-V: KVM: Write hgatp register with valid mode bits
Date: Mon, 18 Aug 2025 13:42:07 +0800 [thread overview]
Message-ID: <20250818054207.21532-1-fangyu.yu@linux.alibaba.com> (raw)
From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
According to the RISC-V Privileged Architecture Spec, when MODE=Bare
is selected,software must write zero to the remaining fields of hgatp.
We have detected the valid mode supported by the HW before, So using a
valid mode to detect how many vmid bits are supported.
Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
---
Changes in v2:
- Fixed build error since kvm_riscv_gstage_mode() has been modified.
---
arch/riscv/kvm/vmid.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/kvm/vmid.c b/arch/riscv/kvm/vmid.c
index 3b426c800480..5f33625f4070 100644
--- a/arch/riscv/kvm/vmid.c
+++ b/arch/riscv/kvm/vmid.c
@@ -14,6 +14,7 @@
#include <linux/smp.h>
#include <linux/kvm_host.h>
#include <asm/csr.h>
+#include <asm/kvm_mmu.h>
#include <asm/kvm_tlb.h>
#include <asm/kvm_vmid.h>
@@ -28,7 +29,7 @@ void __init kvm_riscv_gstage_vmid_detect(void)
/* Figure-out number of VMID bits in HW */
old = csr_read(CSR_HGATP);
- csr_write(CSR_HGATP, old | HGATP_VMID);
+ csr_write(CSR_HGATP, (kvm_riscv_gstage_mode << HGATP_MODE_SHIFT) | HGATP_VMID);
vmid_bits = csr_read(CSR_HGATP);
vmid_bits = (vmid_bits & HGATP_VMID) >> HGATP_VMID_SHIFT;
vmid_bits = fls_long(vmid_bits);
--
2.49.0
WARNING: multiple messages have this Message-ID
From: guoren@kernel.org
To: guoren@kernel.org, troy.mitchell@linux.dev, anup@brainfault.org,
atish.patra@linux.dev, paul.walmsley@sifive.com,
palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr
Cc: fangyu.yu@linux.alibaba.com, guoren@linux.alibaba.com,
kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: [PATCH V2] RISC-V: KVM: Write hgatp register with valid mode bits
Date: Wed, 20 Aug 2025 23:17:19 -0400 [thread overview]
Message-ID: <20250818054207.21532-1-fangyu.yu@linux.alibaba.com> (raw)
Message-ID: <20250821031719.T3mmP-sAPk5MCmdngGZjg9UxcIFtymGaQK6z40vjGHg@z> (raw)
In-Reply-To: <20250821031719.2366017-1-guoren@kernel.org>
From: fangyu.yu@linux.alibaba.com
From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
According to the RISC-V Privileged Architecture Spec, when MODE=Bare
is selected,software must write zero to the remaining fields of hgatp.
We have detected the valid mode supported by the HW before, So using a
valid mode to detect how many vmid bits are supported.
Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
---
Changes in v2:
- Fixed build error since kvm_riscv_gstage_mode() has been modified.
---
arch/riscv/kvm/vmid.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/kvm/vmid.c b/arch/riscv/kvm/vmid.c
index 3b426c800480..5f33625f4070 100644
--- a/arch/riscv/kvm/vmid.c
+++ b/arch/riscv/kvm/vmid.c
@@ -14,6 +14,7 @@
#include <linux/smp.h>
#include <linux/kvm_host.h>
#include <asm/csr.h>
+#include <asm/kvm_mmu.h>
#include <asm/kvm_tlb.h>
#include <asm/kvm_vmid.h>
@@ -28,7 +29,7 @@ void __init kvm_riscv_gstage_vmid_detect(void)
/* Figure-out number of VMID bits in HW */
old = csr_read(CSR_HGATP);
- csr_write(CSR_HGATP, old | HGATP_VMID);
+ csr_write(CSR_HGATP, (kvm_riscv_gstage_mode << HGATP_MODE_SHIFT) | HGATP_VMID);
vmid_bits = csr_read(CSR_HGATP);
vmid_bits = (vmid_bits & HGATP_VMID) >> HGATP_VMID_SHIFT;
vmid_bits = fls_long(vmid_bits);
--
2.49.0
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next reply other threads:[~2025-08-18 5:42 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-18 5:42 fangyu.yu [this message]
2025-08-18 6:17 ` Guo Ren
2025-08-18 7:45 ` Guo Ren
2025-08-19 6:44 ` [PATCH] RISC-V KVM: Remove unnecessary HGATP csr_read guoren
2025-08-21 3:17 ` [PATCH V4 0/3] Fixup & optimize hgatp mode & vmid detect functions guoren
2025-08-21 3:17 ` [PATCH V4 1/3] RISC-V: KVM: Write hgatp register with valid mode bits guoren
2025-08-21 3:17 ` [PATCH V4 2/3] RISC-V: KVM: Remove unnecessary HGATP csr_read guoren
2025-08-21 3:17 ` [PATCH V4 3/3] RISC-V: KVM: Prevent HGATP_MODE_BARE passed guoren
2025-08-18 7:10 ` [PATCH V2] RISC-V: KVM: Write hgatp register with valid mode bits Troy Mitchell
2025-08-19 3:47 ` Nutty.Liu
2025-08-21 3:17 ` guoren
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