From: "Rafael V. Volkmer" <rafael.v.volkmer@gmail.com>
To: rafael.v.volkmer@gmail.com
Cc: linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org,
ukleinek@kernel.org
Subject: [PATCH v5 3/6] pwm: tiehrpwm: refactor AQCTL macros
Date: Fri, 22 Aug 2025 01:45:45 -0300 [thread overview]
Message-ID: <20250822044545.4080-1-rafael.v.volkmer@gmail.com> (raw)
In-Reply-To: <20250822044308.4052-1-rafael.v.volkmer@gmail.com>
Refactor AQCTL polarity/action macros to make channel and count
direction explicit. Keep existing up-count names and add consistent
down-count variants for CAD/CBD events. Centralize action values
(LOW/HIGH/TOGGLE) and reuse them for both channels and directions.
This reduces duplication and makes action selection self-documenting.
No functional change intended.
Signed-off-by: Rafael V. Volkmer <rafael.v.volkmer@gmail.com>
---
drivers/pwm/pwm-tiehrpwm.c | 63 ++++++++++++++++++++++++++------------
1 file changed, 43 insertions(+), 20 deletions(-)
diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c
index d140814a1..b2a55e59b 100644
--- a/drivers/pwm/pwm-tiehrpwm.c
+++ b/drivers/pwm/pwm-tiehrpwm.c
@@ -49,33 +49,56 @@
#define AQSFRC 0x1A
#define AQCSFRC 0x1C
+#define AQCTL_FRCLOW 1
+#define AQCTL_FRCHIGH 2
+#define AQCTL_FRCTOGGLE 3
+
+#define AQCTL_CBD_MASK GENMASK(11, 10)
+#define AQCTL_CBD_FRCLOW FIELD_PREP(AQCTL_CBD_MASK, AQCTL_FRCLOW)
+#define AQCTL_CBD_FRCHIGH FIELD_PREP(AQCTL_CBD_MASK, AQCTL_FRCHIGH)
+#define AQCTL_CBD_FRCTOGGLE FIELD_PREP(AQCTL_CBD_MASK, AQCTL_FRCTOGGLE)
+
#define AQCTL_CBU_MASK GENMASK(9, 8)
-#define AQCTL_CBU_FRCLOW FIELD_PREP(AQCTL_CBU_MASK, 1)
-#define AQCTL_CBU_FRCHIGH FIELD_PREP(AQCTL_CBU_MASK, 2)
-#define AQCTL_CBU_FRCTOGGLE FIELD_PREP(AQCTL_CBU_MASK, 3)
+#define AQCTL_CBU_FRCLOW FIELD_PREP(AQCTL_CBU_MASK, AQCTL_FRCLOW)
+#define AQCTL_CBU_FRCHIGH FIELD_PREP(AQCTL_CBU_MASK, AQCTL_FRCHIGH)
+#define AQCTL_CBU_FRCTOGGLE FIELD_PREP(AQCTL_CBU_MASK, AQCTL_FRCTOGGLE)
+
+#define AQCTL_CAD_MASK GENMASK(7, 6)
+#define AQCTL_CAD_FRCLOW FIELD_PREP(AQCTL_CAD_MASK, AQCTL_FRCLOW)
+#define AQCTL_CAD_FRCHIGH FIELD_PREP(AQCTL_CAD_MASK, AQCTL_FRCHIGH)
+#define AQCTL_CAD_FRCTOGGLE FIELD_PREP(AQCTL_CAD_MASK, AQCTL_FRCTOGGLE)
#define AQCTL_CAU_MASK GENMASK(5, 4)
-#define AQCTL_CAU_FRCLOW FIELD_PREP(AQCTL_CAU_MASK, 1)
-#define AQCTL_CAU_FRCHIGH FIELD_PREP(AQCTL_CAU_MASK, 2)
-#define AQCTL_CAU_FRCTOGGLE FIELD_PREP(AQCTL_CAU_MASK, 3)
+#define AQCTL_CAU_FRCLOW FIELD_PREP(AQCTL_CAU_MASK, AQCTL_FRCLOW)
+#define AQCTL_CAU_FRCHIGH FIELD_PREP(AQCTL_CAU_MASK, AQCTL_FRCHIGH)
+#define AQCTL_CAU_FRCTOGGLE FIELD_PREP(AQCTL_CAU_MASK, AQCTL_FRCTOGGLE)
#define AQCTL_PRD_MASK GENMASK(3, 2)
-#define AQCTL_PRD_FRCLOW FIELD_PREP(AQCTL_PRD_MASK, 1)
-#define AQCTL_PRD_FRCHIGH FIELD_PREP(AQCTL_PRD_MASK, 2)
-#define AQCTL_PRD_FRCTOGGLE FIELD_PREP(AQCTL_PRD_MASK, 3)
+#define AQCTL_PRD_FRCLOW FIELD_PREP(AQCTL_PRD_MASK, AQCTL_FRCLOW)
+#define AQCTL_PRD_FRCHIGH FIELD_PREP(AQCTL_PRD_MASK, AQCTL_FRCHIGH)
+#define AQCTL_PRD_FRCTOGGLE FIELD_PREP(AQCTL_PRD_MASK, AQCTL_FRCTOGGLE)
#define AQCTL_ZRO_MASK GENMASK(1, 0)
-#define AQCTL_ZRO_FRCLOW FIELD_PREP(AQCTL_ZRO_MASK, 1)
-#define AQCTL_ZRO_FRCHIGH FIELD_PREP(AQCTL_ZRO_MASK, 2)
-#define AQCTL_ZRO_FRCTOGGLE FIELD_PREP(AQCTL_ZRO_MASK, 3)
+#define AQCTL_ZRO_FRCLOW FIELD_PREP(AQCTL_ZRO_MASK, AQCTL_FRCLOW)
+#define AQCTL_ZRO_FRCHIGH FIELD_PREP(AQCTL_ZRO_MASK, AQCTL_FRCHIGH)
+#define AQCTL_ZRO_FRCTOGGLE FIELD_PREP(AQCTL_ZRO_MASK, AQCTL_FRCTOGGLE)
+
+#define AQCTL_CHA_UP_POLNORMAL (AQCTL_CAU_FRCLOW | AQCTL_PRD_FRCHIGH | \
+ AQCTL_ZRO_FRCHIGH)
+#define AQCTL_CHA_UP_POLINVERSE (AQCTL_CAU_FRCHIGH | AQCTL_PRD_FRCLOW | \
+ AQCTL_ZRO_FRCLOW)
+#define AQCTL_CHB_UP_POLNORMAL (AQCTL_CBU_FRCLOW | AQCTL_PRD_FRCHIGH | \
+ AQCTL_ZRO_FRCHIGH)
+#define AQCTL_CHB_UP_POLINVERSE (AQCTL_CBU_FRCHIGH | AQCTL_PRD_FRCLOW | \
+ AQCTL_ZRO_FRCLOW)
-#define AQCTL_CHANA_POLNORMAL (AQCTL_CAU_FRCLOW | AQCTL_PRD_FRCHIGH | \
+#define AQCTL_CHA_DN_POLNORMAL (AQCTL_CAD_FRCLOW | AQCTL_PRD_FRCHIGH | \
AQCTL_ZRO_FRCHIGH)
-#define AQCTL_CHANA_POLINVERSED (AQCTL_CAU_FRCHIGH | AQCTL_PRD_FRCLOW | \
+#define AQCTL_CHA_DN_POLINVERSE (AQCTL_CAD_FRCHIGH | AQCTL_PRD_FRCLOW | \
AQCTL_ZRO_FRCLOW)
-#define AQCTL_CHANB_POLNORMAL (AQCTL_CBU_FRCLOW | AQCTL_PRD_FRCHIGH | \
+#define AQCTL_CHB_DN_POLNORMAL (AQCTL_CBD_FRCLOW | AQCTL_PRD_FRCHIGH | \
AQCTL_ZRO_FRCHIGH)
-#define AQCTL_CHANB_POLINVERSED (AQCTL_CBU_FRCHIGH | AQCTL_PRD_FRCLOW | \
+#define AQCTL_CHB_DN_POLINVERSE (AQCTL_CBD_FRCHIGH | AQCTL_PRD_FRCLOW | \
AQCTL_ZRO_FRCLOW)
#define AQSFRC_RLDCSF_MASK GENMASK(7, 6)
@@ -198,17 +221,17 @@ static void configure_polarity(struct ehrpwm_pwm_chip *pc, int chan)
aqctl_mask = AQCTL_CBU_MASK;
if (pc->polarity[chan] == PWM_POLARITY_INVERSED)
- aqctl_val = AQCTL_CHANB_POLINVERSED;
+ aqctl_val = AQCTL_CHB_UP_POLINVERSE;
else
- aqctl_val = AQCTL_CHANB_POLNORMAL;
+ aqctl_val = AQCTL_CHB_UP_POLNORMAL;
} else {
aqctl_reg = AQCTLA;
aqctl_mask = AQCTL_CAU_MASK;
if (pc->polarity[chan] == PWM_POLARITY_INVERSED)
- aqctl_val = AQCTL_CHANA_POLINVERSED;
+ aqctl_val = AQCTL_CHA_UP_POLINVERSE;
else
- aqctl_val = AQCTL_CHANA_POLNORMAL;
+ aqctl_val = AQCTL_CHA_UP_POLNORMAL;
}
aqctl_mask |= AQCTL_PRD_MASK | AQCTL_ZRO_MASK;
--
2.43.0
next prev parent reply other threads:[~2025-08-22 4:46 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-22 4:40 [PATCH v5 1/6] pwm: tiehrpwm: use GENMASK()/FIELD_PREP() for register fields Rafael V. Volkmer
2025-08-22 4:43 ` [PATCH v5 2/6] pwm: tiehrpwm: use FIELD_PREP()/FIELD_GET() for prescalers Rafael V. Volkmer
2025-08-22 4:45 ` Rafael V. Volkmer [this message]
2025-08-22 4:48 ` [PATCH v5 4/6] pwm: tiehrpwm: implement .get_state Rafael V. Volkmer
2025-08-22 4:50 ` [PATCH v5 5/6] pwm: tiehrpwm: account for active channels at probe Rafael V. Volkmer
2025-08-22 4:52 ` [PATCH v5 6/6] pwm: tiehrpwm: tidy prescale calculation style Rafael V. Volkmer
2025-08-25 8:27 ` [PATCH v5 1/6] pwm: tiehrpwm: use GENMASK()/FIELD_PREP() for register fields Uwe Kleine-König
2025-08-26 4:05 ` Rafael V. Volkmer
2025-09-12 9:57 ` Uwe Kleine-König
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