From: Alexander Dahl <ada@thorsis.com>
To: "Sverdlin, Alexander" <alexander.sverdlin@siemens.com>
Cc: "Balamanikandan.Gunasundar@microchip.com"
<Balamanikandan.Gunasundar@microchip.com>,
"miquel.raynal@bootlin.com" <miquel.raynal@bootlin.com>,
"claudiu.beznea@tuxon.dev" <claudiu.beznea@tuxon.dev>,
"nicolas.ferre@microchip.com" <nicolas.ferre@microchip.com>,
"richard@nod.at" <richard@nod.at>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"vigneshr@ti.com" <vigneshr@ti.com>,
"alexandre.belloni@bootlin.com" <alexandre.belloni@bootlin.com>,
"linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
"bbrezillon@kernel.org" <bbrezillon@kernel.org>,
"stable@vger.kernel.org" <stable@vger.kernel.org>
Subject: Re: [PATCH v2] mtd: nand: raw: atmel: Respect tAR, tCLR in read setup timing
Date: Mon, 25 Aug 2025 15:22:29 +0200 [thread overview]
Message-ID: <20250825-vista-cuddle-c159a6bd97ec@thorsis.com> (raw)
In-Reply-To: <3d0259caac9925e3d5dd3dd27a6785b2a2e82c0b.camel@siemens.com>
Hello Alexander,
Am Mon, Aug 25, 2025 at 12:21:24PM +0000 schrieb Sverdlin, Alexander:
> Hi Alexander,
>
> On Mon, 2025-08-25 at 13:02 +0200, Alexander Dahl wrote:
> > > Having setup time 0 violates tAR, tCLR of some chips, for instance
> > > TOSHIBA TC58NVG2S3ETAI0 cannot be detected successfully (first ID byte
> > > being read duplicated, i.e. 98 98 dc 90 15 76 14 03 instead of
> > > 98 dc 90 15 76 ...).
> > >
> > > Atmel Application Notes postulated 1 cycle NRD_SETUP without explanation
> > > [1], but it looks more appropriate to just calculate setup time properly.
> > >
> > > [1] Link: https://ww1.microchip.com/downloads/aemDocuments/documents/MPU32/ApplicationNotes/ApplicationNotes/doc6255.pdf
> > > Cc: stable@vger.kernel.org
> > > Fixes: f9ce2eddf176 ("mtd: nand: atmel: Add ->setup_data_interface() hooks")
> > > Signed-off-by: Alexander Sverdlin <alexander.sverdlin@siemens.com>
> >
> > Tested-by: Alexander Dahl <ada@thorsis.com>
> >
> > Threw this on top of 6.12.39-rt11 and tested on two custom platforms
> > both with a Spansion S34ML02G1 SLC 2GBit flash chip, but with
> > different SoCs (sama5d2, sam9x60). We had difficulties with the
> > timing of those NAND flash chips in the past and I wanted to make sure
> > this patch does not break our setup. Seems fine in a quick test,
> > reading and writing and reading back is successful.
>
> thank you for your feedback!
>
> Do you see an opportunity to drop the downstream timing quirks with my patch?
Which downstream do you refer to?
> I actually have another patch related to timings, but it's based on code-review
> only and the theoretical issue never manifested itself in practice on our side...
I also have another one, for which fixes got merged in at91bootstrap
and U-Boot already, but I never found the time to upstream it on
Linux. It's related to pulse timing.
> (it's about missing ndelay at the end of atmel_smc_nand_exec_instr())
That does not ring a bell here, sorry.
Greets
Alex
next prev parent reply other threads:[~2025-08-25 13:22 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-21 12:00 A. Sverdlin
2025-08-25 11:02 ` Alexander Dahl
2025-08-25 12:21 ` Sverdlin, Alexander
2025-08-25 13:22 ` Alexander Dahl [this message]
2025-08-25 13:41 ` Sverdlin, Alexander
2025-08-26 10:44 ` Alexander Dahl
2025-09-01 12:26 ` Miquel Raynal
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