Re: [PATCH v2] mtd: nand: raw: atmel: Respect tAR, tCLR in read setup timing

[Alexander Dahl <ada@thorsis.com>]

Hello Alexander,

Am Mon, Aug 25, 2025 at 01:41:05PM +0000 schrieb Sverdlin, Alexander:
> Hi Alexander,
> 
> On Mon, 2025-08-25 at 15:22 +0200, Alexander Dahl wrote:
> > > > Threw this on top of 6.12.39-rt11 and tested on two custom platforms
> > > > both with a Spansion S34ML02G1 SLC 2GBit flash chip, but with
> > > > different SoCs (sama5d2, sam9x60).  We had difficulties with the
>                                           ^^^^^^^^^^^^^^^^^^^
> [*]
> 
> > > > timing of those NAND flash chips in the past and I wanted to make sure
> > > > this patch does not break our setup.  Seems fine in a quick test,
> > > > reading and writing and reading back is successful.
> > > 
> > > thank you for your feedback!
> > > 
> > > Do you see an opportunity to drop the downstream timing quirks with my patch?
> > 
> > Which downstream do you refer to?
> 
> That's how I understood the phrase above, that some adjustments are still required
> on your side additionally to standard timings. Sorry for the confusion, if it turns
> out to be a misunderstanding on my side!

I don't think your patch is sufficient to solve our problems with
sam9x60 and S34ML02G1.  Different parts of the timings are affected.
You changed NRD_SETUP while I changed NRD_PULSE.  I just wanted to
make sure both patches do not interfere.

For reference, these are the changes in at91bootstrap and u-boot I
referred to:

https://github.com/linux4sam/at91bootstrap/issues/174
https://github.com/linux4sam/at91bootstrap/commit/e2dfd8141d00613a37acee66ef5724f70f34a538

https://source.denx.de/u-boot/u-boot/-/commit/344e2f2cd4a407f847b301804f37d036e8a0a10c

My problem might be fixed with commit f552a7c7e0a1 ("mtd: rawnand:
atmel: set pmecc data setup time"), but I did not have time to test
that assumption.

Sorry for the confusion.

Greets
Alex