From: Mark Brown <broonie@kernel.org>
To: Marc Zyngier <maz@kernel.org>,
Oliver Upton <oliver.upton@linux.dev>,
Joey Gouly <joey.gouly@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Will Deacon <will@kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Jonathan Corbet <corbet@lwn.net>, Shuah Khan <shuah@kernel.org>
Cc: Dave Martin <Dave.Martin@arm.com>, Fuad Tabba <tabba@google.com>,
Mark Rutland <mark.rutland@arm.com>,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org,
Peter Maydell <peter.maydell@linaro.org>,
Eric Auger <eric.auger@redhat.com>,
Mark Brown <broonie@kernel.org>
Subject: [PATCH v8 17/29] KVM: arm64: Support TPIDR2_EL0
Date: Tue, 02 Sep 2025 12:36:20 +0100 [thread overview]
Message-ID: <20250902-kvm-arm64-sme-v8-17-2cb2199c656c@kernel.org> (raw)
In-Reply-To: <20250902-kvm-arm64-sme-v8-0-2cb2199c656c@kernel.org>
SME adds a new thread ID register, TPIDR2_EL0. This is used in userspace
for delayed saving of the ZA state but in terms of the architecture is
not really connected to SME other than being part of FEAT_SME. It has an
independent fine grained trap and the runtime connection with the rest
of SME is purely software defined.
Expose the register as a system register if the guest supports SME,
context switching it along with the other EL0 TPIDRs.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/kvm_host.h | 1 +
arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 15 +++++++++++++++
arch/arm64/kvm/sys_regs.c | 3 ++-
3 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index edb2acdb4bd1..632c74397fa9 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -450,6 +450,7 @@ enum vcpu_sysreg {
CSSELR_EL1, /* Cache Size Selection Register */
TPIDR_EL0, /* Thread ID, User R/W */
TPIDRRO_EL0, /* Thread ID, User R/O */
+ TPIDR2_EL0, /* Thread ID, Register 2 */
TPIDR_EL1, /* Thread ID, Privileged */
CNTKCTL_EL1, /* Timer Control Register (EL1) */
PAR_EL1, /* Physical Address Register */
diff --git a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h
index 5624fd705ae3..8c3b3d6df99f 100644
--- a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h
+++ b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h
@@ -88,6 +88,17 @@ static inline bool ctxt_has_sctlr2(struct kvm_cpu_context *ctxt)
return kvm_has_sctlr2(kern_hyp_va(vcpu->kvm));
}
+static inline bool ctxt_has_sme(struct kvm_cpu_context *ctxt)
+{
+ struct kvm_vcpu *vcpu;
+
+ if (!system_supports_sme())
+ return false;
+
+ vcpu = ctxt_to_vcpu(ctxt);
+ return kvm_has_sme(kern_hyp_va(vcpu->kvm));
+}
+
static inline bool ctxt_is_guest(struct kvm_cpu_context *ctxt)
{
return host_data_ptr(host_ctxt) != ctxt;
@@ -127,6 +138,8 @@ static inline void __sysreg_save_user_state(struct kvm_cpu_context *ctxt)
{
ctxt_sys_reg(ctxt, TPIDR_EL0) = read_sysreg(tpidr_el0);
ctxt_sys_reg(ctxt, TPIDRRO_EL0) = read_sysreg(tpidrro_el0);
+ if (ctxt_has_sme(ctxt))
+ ctxt_sys_reg(ctxt, TPIDR2_EL0) = read_sysreg_s(SYS_TPIDR2_EL0);
}
static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt)
@@ -204,6 +217,8 @@ static inline void __sysreg_restore_user_state(struct kvm_cpu_context *ctxt)
{
write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL0), tpidr_el0);
write_sysreg(ctxt_sys_reg(ctxt, TPIDRRO_EL0), tpidrro_el0);
+ if (ctxt_has_sme(ctxt))
+ write_sysreg_s(ctxt_sys_reg(ctxt, TPIDR2_EL0), SYS_TPIDR2_EL0);
}
static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt,
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 81742e9237c0..4166d396450d 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -3243,7 +3243,8 @@ static const struct sys_reg_desc sys_reg_descs[] = {
.visibility = s1poe_visibility },
{ SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
{ SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
- { SYS_DESC(SYS_TPIDR2_EL0), undef_access },
+ { SYS_DESC(SYS_TPIDR2_EL0), NULL, reset_unknown, TPIDR2_EL0,
+ .visibility = sme_visibility},
{ SYS_DESC(SYS_SCXTNUM_EL0), undef_access },
--
2.39.5
next prev parent reply other threads:[~2025-09-02 11:45 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-02 11:36 [PATCH v8 00/29] KVM: arm64: Implement support for SME Mark Brown
2025-09-02 11:36 ` [PATCH v8 01/29] arm64/sysreg: Update SMIDR_EL1 to DDI0601 2025-06 Mark Brown
2025-09-02 11:36 ` [PATCH v8 02/29] arm64/fpsimd: Update FA64 and ZT0 enables when loading SME state Mark Brown
2025-09-02 11:36 ` [PATCH v8 03/29] arm64/fpsimd: Decide to save ZT0 and streaming mode FFR at bind time Mark Brown
2025-09-02 11:36 ` [PATCH v8 04/29] arm64/fpsimd: Check enable bit for FA64 when saving EFI state Mark Brown
2025-09-02 11:36 ` [PATCH v8 05/29] arm64/fpsimd: Determine maximum virtualisable SME vector length Mark Brown
2025-09-02 11:36 ` [PATCH v8 06/29] KVM: arm64: Introduce non-UNDEF FGT control Mark Brown
2025-09-19 15:14 ` Marc Zyngier
2025-09-19 15:53 ` Mark Brown
2025-09-02 11:36 ` [PATCH v8 07/29] KVM: arm64: Pay attention to FFR parameter in SVE save and load Mark Brown
2025-09-02 11:36 ` [PATCH v8 08/29] KVM: arm64: Pull ctxt_has_ helpers to start of sysreg-sr.h Mark Brown
2025-09-02 11:36 ` [PATCH v8 09/29] KVM: arm64: Move SVE state access macros after feature test macros Mark Brown
2025-09-02 11:36 ` [PATCH v8 10/29] KVM: arm64: Rename SVE finalization constants to be more general Mark Brown
2025-09-02 11:36 ` [PATCH v8 11/29] KVM: arm64: Document the KVM ABI for SME Mark Brown
2025-11-24 15:48 ` Peter Maydell
2025-11-24 20:12 ` Mark Brown
2025-11-26 17:23 ` Dave Martin
2025-11-26 18:41 ` Mark Brown
2025-11-27 15:06 ` Peter Maydell
2025-11-27 15:47 ` Mark Brown
2025-09-02 11:36 ` [PATCH v8 12/29] KVM: arm64: Define internal features " Mark Brown
2025-09-02 11:36 ` [PATCH v8 13/29] KVM: arm64: Rename sve_state_reg_region Mark Brown
2025-09-02 11:36 ` [PATCH v8 14/29] KVM: arm64: Store vector lengths in an array Mark Brown
2025-09-02 11:36 ` [PATCH v8 15/29] KVM: arm64: Implement SME vector length configuration Mark Brown
2025-09-02 11:36 ` [PATCH v8 16/29] KVM: arm64: Support SME control registers Mark Brown
2025-09-02 11:36 ` Mark Brown [this message]
2025-09-02 11:36 ` [PATCH v8 18/29] KVM: arm64: Support SME identification registers for guests Mark Brown
2025-09-02 11:36 ` [PATCH v8 19/29] KVM: arm64: Support SME priority registers Mark Brown
2025-09-02 11:36 ` [PATCH v8 20/29] KVM: arm64: Provide assembly for SME register access Mark Brown
2025-09-02 11:36 ` [PATCH v8 21/29] KVM: arm64: Support userspace access to streaming mode Z and P registers Mark Brown
2025-09-02 11:36 ` [PATCH v8 22/29] KVM: arm64: Flush register state on writes to SVCR.SM and SVCR.ZA Mark Brown
2025-09-02 11:36 ` [PATCH v8 23/29] KVM: arm64: Expose SME specific state to userspace Mark Brown
2025-09-02 11:36 ` [PATCH v8 24/29] KVM: arm64: Context switch SME state for guests Mark Brown
2025-09-02 11:36 ` [PATCH v8 25/29] KVM: arm64: Handle SME exceptions Mark Brown
2025-09-02 11:36 ` [PATCH v8 26/29] KVM: arm64: Expose SME to nested guests Mark Brown
2025-09-02 11:36 ` [PATCH v8 27/29] KVM: arm64: Provide interface for configuring and enabling SME for guests Mark Brown
2025-09-02 11:36 ` [PATCH v8 28/29] KVM: arm64: selftests: Add SME system registers to get-reg-list Mark Brown
2025-09-02 11:36 ` [PATCH v8 29/29] KVM: arm64: selftests: Add SME to set_id_regs test Mark Brown
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