From: Akhil P Oommen <akhilpo@oss.qualcomm.com>
To: Rob Clark <robin.clark@oss.qualcomm.com>,
Sean Paul <sean@poorly.run>,
Konrad Dybcio <konradybcio@kernel.org>,
Dmitry Baryshkov <lumag@kernel.org>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Jessica Zhang <jessica.zhang@oss.qualcomm.com>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Antonino Maniscalco <antomani103@gmail.com>,
Neil Armstrong <neil.armstrong@linaro.org>
Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org,
Akhil P Oommen <akhilpo@oss.qualcomm.com>
Subject: [PATCH v2 01/16] drm/msm: Update GMU register xml
Date: Mon, 08 Sep 2025 13:56:54 +0530 [thread overview]
Message-ID: <20250908-ifpc-support-v2-1-631b1080bf91@oss.qualcomm.com> (raw)
In-Reply-To: <20250908-ifpc-support-v2-0-631b1080bf91@oss.qualcomm.com>
Update GMU register xml with additional definitions for a7x family.
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
index 3d2cc339b8f19c8d24b2c9144569b2364afc5ebc..b15a242d974d6b42133171c8484d3b0413f2d3a4 100644
--- a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
+++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
@@ -99,6 +99,10 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<bitfield name="GX_HM_GDSC_POWER_OFF" pos="6" type="boolean"/>
<bitfield name="GX_HM_CLK_OFF" pos="7" type="boolean"/>
</reg32>
+ <reg32 offset="0x50d0" name="GMU_SPTPRAC_PWR_CLK_STATUS" variants="A7XX">
+ <bitfield name="GX_HM_GDSC_POWER_OFF" pos="0" type="boolean"/>
+ <bitfield name="GX_HM_CLK_OFF" pos="1" type="boolean"/>
+ </reg32>
<reg32 offset="0x50e4" name="GMU_GPU_NAP_CTRL">
<bitfield name="HW_NAP_ENABLE" pos="0"/>
<bitfield name="SID" low="4" high="8"/>
@@ -127,6 +131,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<reg32 offset="0x5088" name="GMU_ALWAYS_ON_COUNTER_L"/>
<reg32 offset="0x5089" name="GMU_ALWAYS_ON_COUNTER_H"/>
<reg32 offset="0x50c3" name="GMU_GMU_PWR_COL_KEEPALIVE"/>
+ <reg32 offset="0x50c4" name="GMU_PWR_COL_PREEMPT_KEEPALIVE"/>
<reg32 offset="0x5180" name="GMU_HFI_CTRL_STATUS"/>
<reg32 offset="0x5181" name="GMU_HFI_VERSION_INFO"/>
<reg32 offset="0x5182" name="GMU_HFI_SFR_ADDR"/>
@@ -228,6 +233,12 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<reg32 offset="0x03ee" name="RSCC_TCS1_DRV0_STATUS"/>
<reg32 offset="0x0496" name="RSCC_TCS2_DRV0_STATUS"/>
<reg32 offset="0x053e" name="RSCC_TCS3_DRV0_STATUS"/>
+ <reg32 offset="0x05e6" name="RSCC_TCS4_DRV0_STATUS" variants="A7XX"/>
+ <reg32 offset="0x068e" name="RSCC_TCS5_DRV0_STATUS" variants="A7XX"/>
+ <reg32 offset="0x0736" name="RSCC_TCS6_DRV0_STATUS" variants="A7XX"/>
+ <reg32 offset="0x07de" name="RSCC_TCS7_DRV0_STATUS" variants="A7XX"/>
+ <reg32 offset="0x0886" name="RSCC_TCS8_DRV0_STATUS" variants="A7XX"/>
+ <reg32 offset="0x092e" name="RSCC_TCS9_DRV0_STATUS" variants="A7XX"/>
</domain>
</database>
--
2.50.1
next prev parent reply other threads:[~2025-09-08 8:27 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-08 8:26 [PATCH v2 00/16] drm/msm: Support for Inter Frame Power Collapse (IFPC) feature Akhil P Oommen
2025-09-08 8:26 ` Akhil P Oommen [this message]
2025-09-08 8:26 ` [PATCH v2 02/16] drm/msm: a6xx: Fix gx_is_on check for a7x family Akhil P Oommen
2025-09-08 8:26 ` [PATCH v2 03/16] drm/msm/a6xx: Poll additional DRV status Akhil P Oommen
2025-09-08 15:18 ` Konrad Dybcio
2025-09-08 16:49 ` Akhil P Oommen
2025-09-08 8:26 ` [PATCH v2 04/16] drm/msm/a6xx: Fix PDC sleep sequence Akhil P Oommen
2025-09-08 8:26 ` [PATCH v2 05/16] drm/msm: a6xx: Refactor a6xx_sptprac_enable() Akhil P Oommen
2025-09-08 15:21 ` Konrad Dybcio
2025-09-08 8:26 ` [PATCH v2 06/16] drm/msm: Add an ftrace for gpu register access Akhil P Oommen
2025-09-08 8:27 ` [PATCH v2 07/16] drm/msm/adreno: Add fenced regwrite support Akhil P Oommen
2025-09-08 15:37 ` Konrad Dybcio
2025-09-08 16:15 ` Akhil P Oommen
2025-09-08 15:54 ` Connor Abbott
2025-09-08 16:46 ` Akhil P Oommen
2025-09-08 8:27 ` [PATCH v2 08/16] drm/msm/a6xx: Set Keep-alive votes to block IFPC Akhil P Oommen
2025-09-08 8:27 ` [PATCH v2 09/16] drm/msm/a6xx: Switch to GMU AO counter Akhil P Oommen
2025-09-08 8:27 ` [PATCH v2 10/16] drm/msm/a6xx: Poll AHB fence status in GPU IRQ handler Akhil P Oommen
2025-09-08 8:27 ` [PATCH v2 11/16] drm/msm: Add support for IFPC Akhil P Oommen
2025-09-08 8:27 ` [PATCH v2 12/16] drm/msm/a6xx: Fix hangcheck " Akhil P Oommen
2025-09-08 8:27 ` [PATCH v2 13/16] drm/msm/adreno: Disable IFPC when sysprof is active Akhil P Oommen
2025-09-08 8:27 ` [PATCH v2 14/16] drm/msm/a6xx: Make crashstate capture IFPC safe Akhil P Oommen
2025-09-08 8:27 ` [PATCH v2 15/16] drm/msm/a6xx: Enable IFPC on Adreno X1-85 Akhil P Oommen
2025-09-08 15:24 ` Konrad Dybcio
2025-10-31 23:43 ` Chia-I Wu
2025-11-01 12:57 ` Rob Clark
2025-11-01 19:52 ` Akhil P Oommen
2025-11-02 17:55 ` Chia-I Wu
2025-11-03 15:11 ` Akhil P Oommen
2025-09-08 8:27 ` [PATCH v2 16/16] drm/msm/a6xx: Enable IFPC on A750 GPU Akhil P Oommen
2025-09-08 17:11 ` [PATCH v2 00/16] drm/msm: Support for Inter Frame Power Collapse (IFPC) feature Neil Armstrong
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