* [PATCH 0/2] Add pinctrl support for the Axis ARTPEC-9 SoC [not found] <CGME20250917070036epcas5p15db06286fc187651574b68ea4ebe5edb@epcas5p1.samsung.com> @ 2025-09-17 7:00 ` Ravi Patel [not found] ` <CGME20250917070041epcas5p4729ea496eee0c1ec2f4c234a63f71f7d@epcas5p4.samsung.com> ` (2 more replies) 0 siblings, 3 replies; 5+ messages in thread From: Ravi Patel @ 2025-09-17 7:00 UTC (permalink / raw) To: krzk, s.nawrocki, alim.akhtar, linus.walleij, robh, conor+dt Cc: tomasz.figa, linux-arm-kernel, linux-samsung-soc, linux-gpio, devicetree, linux-kernel, ksk4725, pjsin865, gwk1013, bread, jspark, limjh0823, lightwise, hgkim05, mingyoungbo, smn1196, shradha.t, swathi.ks, kenkim, Ravi Patel Add pinctrl bindings and driver data for the Axis ARTPEC-9 SoC. Axis ARTPEC-9 SoC contains 6-core Cortex-A55 CPU and other several IPs. This SoC is an Axis-designed chipset used in surveillance camera products. This ARTPEC-9 SoC has a variety of Samsung-specific IP blocks and Axis-specific IP blocks and SoC is manufactured by Samsung Foundry. NOTE: These 2 patches has been separated from the original ARTPEC-9 base patch series as the target branch is different. Target branch: Samsung pinctrl Linux kernel tree SeonGu Kang (2): dt-bindings: pinctrl: samsung: Add compatible for ARTPEC-9 SoC pinctrl: samsung: Add ARTPEC-9 SoC specific configuration .../bindings/pinctrl/samsung,pinctrl.yaml | 1 + .../pinctrl/samsung/pinctrl-exynos-arm64.c | 49 +++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 4 files changed, 53 insertions(+) -- 2.17.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
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* [PATCH 1/2] dt-bindings: pinctrl: samsung: Add compatible for ARTPEC-9 SoC [not found] ` <CGME20250917070041epcas5p4729ea496eee0c1ec2f4c234a63f71f7d@epcas5p4.samsung.com> @ 2025-09-17 7:00 ` Ravi Patel 2025-09-17 19:29 ` Conor Dooley 0 siblings, 1 reply; 5+ messages in thread From: Ravi Patel @ 2025-09-17 7:00 UTC (permalink / raw) To: krzk, s.nawrocki, alim.akhtar, linus.walleij, robh, conor+dt Cc: tomasz.figa, linux-arm-kernel, linux-samsung-soc, linux-gpio, devicetree, linux-kernel, ksk4725, pjsin865, gwk1013, bread, jspark, limjh0823, lightwise, hgkim05, mingyoungbo, smn1196, shradha.t, swathi.ks, kenkim, Ravi Patel From: SeonGu Kang <ksk4725@coasia.com> Document the compatible string for ARTPEC-9 SoC pinctrl block, which is similar to other Samsung SoC pinctrl blocks. Signed-off-by: SeonGu Kang <ksk4725@coasia.com> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> --- Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml index f1094d65e846..a2c16385bad3 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -36,6 +36,7 @@ properties: compatible: enum: - axis,artpec8-pinctrl + - axis,artpec9-pinctrl - google,gs101-pinctrl - samsung,s3c64xx-pinctrl - samsung,s5pv210-pinctrl -- 2.17.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] dt-bindings: pinctrl: samsung: Add compatible for ARTPEC-9 SoC 2025-09-17 7:00 ` [PATCH 1/2] dt-bindings: pinctrl: samsung: Add compatible for " Ravi Patel @ 2025-09-17 19:29 ` Conor Dooley 0 siblings, 0 replies; 5+ messages in thread From: Conor Dooley @ 2025-09-17 19:29 UTC (permalink / raw) To: Ravi Patel Cc: krzk, s.nawrocki, alim.akhtar, linus.walleij, robh, conor+dt, tomasz.figa, linux-arm-kernel, linux-samsung-soc, linux-gpio, devicetree, linux-kernel, ksk4725, pjsin865, gwk1013, bread, jspark, limjh0823, lightwise, hgkim05, mingyoungbo, smn1196, shradha.t, swathi.ks, kenkim [-- Attachment #1: Type: text/plain, Size: 52 bytes --] Acked-by: Conor Dooley <conor.dooley@microchip.com> [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 5+ messages in thread
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* [PATCH 2/2] pinctrl: samsung: Add ARTPEC-9 SoC specific configuration [not found] ` <CGME20250917070044epcas5p4562c860c2ff5a3f848a91aa619c3a610@epcas5p4.samsung.com> @ 2025-09-17 7:00 ` Ravi Patel 0 siblings, 0 replies; 5+ messages in thread From: Ravi Patel @ 2025-09-17 7:00 UTC (permalink / raw) To: krzk, s.nawrocki, alim.akhtar, linus.walleij, robh, conor+dt Cc: tomasz.figa, linux-arm-kernel, linux-samsung-soc, linux-gpio, devicetree, linux-kernel, ksk4725, pjsin865, gwk1013, bread, jspark, limjh0823, lightwise, hgkim05, mingyoungbo, smn1196, shradha.t, swathi.ks, kenkim, Ravi Patel From: SeonGu Kang <ksk4725@coasia.com> Add Axis ARTPEC-9 SoC specific configuration data to enable pinctrl. Signed-off-by: SeonGu Kang <ksk4725@coasia.com> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> --- .../pinctrl/samsung/pinctrl-exynos-arm64.c | 49 +++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 3 files changed, 52 insertions(+) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index 323487dfa8c2..5a64fb428142 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -1866,3 +1866,52 @@ const struct samsung_pinctrl_of_match_data artpec8_of_data __initconst = { .ctrl = artpec8_pin_ctrl, .num_ctrl = ARRAY_SIZE(artpec8_pin_ctrl), }; + +/* pin banks of artpec9 pin-controller (FSYS0) */ +static const struct samsung_pin_bank_data artpec9_pin_banks0[] __initconst = { + ARTPEC_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00), + ARTPEC_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04), + ARTPEC_PIN_BANK_EINTG(8, 0x040, "gpe0", 0x08), + ARTPEC_PIN_BANK_EINTG(8, 0x060, "gpe1", 0x0c), + ARTPEC_PIN_BANK_EINTG(8, 0x080, "gpe2", 0x10), + ARTPEC_PIN_BANK_EINTG(8, 0x0a0, "gpe3", 0x14), + ARTPEC_PIN_BANK_EINTG(2, 0x0c0, "gpe4", 0x18), + ARTPEC_PIN_BANK_EINTG(8, 0x0e0, "gps0", 0x1c), + ARTPEC_PIN_BANK_EINTG(8, 0x100, "gps1", 0x20), + ARTPEC_PIN_BANK_EINTG(5, 0x120, "gpi0", 0x24), +}; + +/* pin banks of artpec9 pin-controller (FSYS1) */ +static const struct samsung_pin_bank_data artpec9_pin_banks1[] __initconst = { + ARTPEC_PIN_BANK_EINTG(2, 0x000, "gpu0", 0x00), +}; + +/* pin banks of artpec9 pin-controller (PERIC) */ +static const struct samsung_pin_bank_data artpec9_pin_banks2[] __initconst = { + ARTPEC_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + ARTPEC_PIN_BANK_EINTG(8, 0x020, "gpa1", 0x04), +}; + +static const struct samsung_pin_ctrl artpec9_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 FSYS0 data */ + .pin_banks = artpec9_pin_banks0, + .nr_banks = ARRAY_SIZE(artpec9_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 1 FSYS1 data */ + .pin_banks = artpec9_pin_banks1, + .nr_banks = ARRAY_SIZE(artpec9_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 2 PERIC data */ + .pin_banks = artpec9_pin_banks2, + .nr_banks = ARRAY_SIZE(artpec9_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + }, +}; + +const struct samsung_pinctrl_of_match_data artpec9_of_data __initconst = { + .ctrl = artpec9_pin_ctrl, + .num_ctrl = ARRAY_SIZE(artpec9_pin_ctrl), +}; diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index c099195fc464..1d978443bd1b 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1484,6 +1484,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { #ifdef CONFIG_PINCTRL_EXYNOS_ARM64 { .compatible = "axis,artpec8-pinctrl", .data = &artpec8_of_data }, + { .compatible = "axis,artpec9-pinctrl", + .data = &artpec9_of_data }, { .compatible = "google,gs101-pinctrl", .data = &gs101_of_data }, { .compatible = "samsung,exynos2200-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index 3e8ef91d94a3..94334bd860ca 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -382,6 +382,7 @@ struct samsung_pmx_func { /* list of all exported SoC specific data */ extern const struct samsung_pinctrl_of_match_data artpec8_of_data; +extern const struct samsung_pinctrl_of_match_data artpec9_of_data; extern const struct samsung_pinctrl_of_match_data exynos2200_of_data; extern const struct samsung_pinctrl_of_match_data exynos3250_of_data; extern const struct samsung_pinctrl_of_match_data exynos4210_of_data; -- 2.17.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 0/2] Add pinctrl support for the Axis ARTPEC-9 SoC 2025-09-17 7:00 ` [PATCH 0/2] Add pinctrl support for the Axis ARTPEC-9 SoC Ravi Patel [not found] ` <CGME20250917070041epcas5p4729ea496eee0c1ec2f4c234a63f71f7d@epcas5p4.samsung.com> [not found] ` <CGME20250917070044epcas5p4562c860c2ff5a3f848a91aa619c3a610@epcas5p4.samsung.com> @ 2025-10-13 1:03 ` Krzysztof Kozlowski 2 siblings, 0 replies; 5+ messages in thread From: Krzysztof Kozlowski @ 2025-10-13 1:03 UTC (permalink / raw) To: krzk, s.nawrocki, alim.akhtar, linus.walleij, robh, conor+dt, Ravi Patel Cc: tomasz.figa, linux-arm-kernel, linux-samsung-soc, linux-gpio, devicetree, linux-kernel, ksk4725, pjsin865, gwk1013, bread, jspark, limjh0823, lightwise, hgkim05, mingyoungbo, smn1196, shradha.t, swathi.ks, kenkim On Wed, 17 Sep 2025 12:30:02 +0530, Ravi Patel wrote: > Add pinctrl bindings and driver data for the Axis ARTPEC-9 SoC. > > Axis ARTPEC-9 SoC contains 6-core Cortex-A55 CPU and other several IPs. > This SoC is an Axis-designed chipset used in surveillance camera products. > > This ARTPEC-9 SoC has a variety of Samsung-specific IP blocks and > Axis-specific IP blocks and SoC is manufactured by Samsung Foundry. > > [...] Applied, thanks! [1/2] dt-bindings: pinctrl: samsung: Add compatible for ARTPEC-9 SoC https://git.kernel.org/pinctrl/samsung/c/e671a1bb5d1cf9ca4dbab61b9a3e1e77579f99ba [2/2] pinctrl: samsung: Add ARTPEC-9 SoC specific configuration https://git.kernel.org/pinctrl/samsung/c/3cfc60e09bdc95483875f0b63cfdc23aea67135b Best regards, -- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> ^ permalink raw reply [flat|nested] 5+ messages in thread
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2025-09-17 7:00 ` [PATCH 0/2] Add pinctrl support for the Axis ARTPEC-9 SoC Ravi Patel
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2025-09-17 7:00 ` [PATCH 1/2] dt-bindings: pinctrl: samsung: Add compatible for " Ravi Patel
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2025-09-17 7:00 ` [PATCH 2/2] pinctrl: samsung: Add ARTPEC-9 SoC specific configuration Ravi Patel
2025-10-13 1:03 ` [PATCH 0/2] Add pinctrl support for the Axis ARTPEC-9 SoC Krzysztof Kozlowski
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