* [PATCH v2 0/4] rpmh-regulators: Update rpmh-regulator driver and dt-bindings for Glymur
@ 2025-09-16 12:58 Kamal Wadhwa
2025-09-16 12:58 ` [PATCH v2 1/4] dt-bindings: rpmh-regulator : Add compatibles for PMH01XX & PMCX0102 Kamal Wadhwa
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Kamal Wadhwa @ 2025-09-16 12:58 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, dmitry.baryshkov, konrad.dybcio
Cc: linux-arm-msm, Krzysztof Kozlowski, linux-kernel, devicetree,
Kamal Wadhwa, jishnu.prakash
This series contains patches to update rpmh-regulator driver and
dt-bindings for supporting the PMIC voltage regulators present on the
boards with Qualcomm's next gen compute SoC - Glymur.
Device tree changes aren't part of this series and will be posted
separately after the official announcement of the Glymur SoC.
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
---
Changes in v2:
- Updated pmic-id dt binding's change commit message to elaborate `why` the
dt-binding change is needed
- Updated commit message for driver change related to new resource name patch
to clarify that `resource name` refers to `cmd-db resource names`.
- Link to v1: https://lore.kernel.org/r/20250916-glymur-rpmh-regulator-driver-v1-0-bb9b00e93a61@oss.qualcomm.com
---
Kamal Wadhwa (4):
dt-bindings: rpmh-regulator : Add compatibles for PMH01XX & PMCX0102
dt-bindings: rpmh-regulator: Update pmic-id property description
regulator: rpmh-regulator: Add support for new resource name format
regulator: rpmh-regulator: Add RPMH regulator support for Glymur
.../bindings/regulator/qcom,rpmh-regulator.yaml | 39 +-
drivers/regulator/qcom-rpmh-regulator.c | 1322 ++++++++++++--------
2 files changed, 811 insertions(+), 550 deletions(-)
---
base-commit: c3067c2c38316c3ef013636c93daa285ee6aaa2e
change-id: 20250916-glymur-rpmh-regulator-driver-80c9543cdd6e
Best regards,
--
Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 1/4] dt-bindings: rpmh-regulator : Add compatibles for PMH01XX & PMCX0102
2025-09-16 12:58 [PATCH v2 0/4] rpmh-regulators: Update rpmh-regulator driver and dt-bindings for Glymur Kamal Wadhwa
@ 2025-09-16 12:58 ` Kamal Wadhwa
2025-09-16 12:58 ` [PATCH v2 2/4] dt-bindings: rpmh-regulator: Update pmic-id property description Kamal Wadhwa
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Kamal Wadhwa @ 2025-09-16 12:58 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, dmitry.baryshkov, konrad.dybcio
Cc: linux-arm-msm, Krzysztof Kozlowski, linux-kernel, devicetree,
Kamal Wadhwa, jishnu.prakash
Add rpmh-regulator driver compatibles strings for below PMICs:
- PMH0101
- PMH0104
- PMH0110
- PMCX0102
Also add the supply name properties for the regulators
present on these PMICs.
Co-developed-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
---
.../bindings/regulator/qcom,rpmh-regulator.yaml | 37 ++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml b/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml
index 4c5b0629aa3e622579b54a226785139a0b986079..40e57b10ebbebeff130871b6d978df64111b6f29 100644
--- a/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml
+++ b/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml
@@ -51,8 +51,12 @@ description: |
For PM8450, smps1 - smps6, ldo1 - ldo4
For PM8550, smps1 - smps6, ldo1 - ldo17, bob1 - bob2
For PM8998, smps1 - smps13, ldo1 - ldo28, lvs1 - lvs2
+ For PMH0101, ldo1 - ldo18, bob1 - bob2
+ For PMH0104, smps1 - smps4
+ For PMH0110, smps1 - smps10, ldo1 - ldo4
For PMI8998, bob
For PMC8380, smps1 - smps8, ldo1 - lodo3
+ For PMCX0102, smps1 - smps10, ldo1 - ldo4
For PMR735A, smps1 - smps3, ldo1 - ldo7
For PMR735B, ldo1 - ldo12
For PMX55, smps1 - smps7, ldo1 - ldo16
@@ -85,7 +89,11 @@ properties:
- qcom,pmc8180-rpmh-regulators
- qcom,pmc8180c-rpmh-regulators
- qcom,pmc8380-rpmh-regulators
+ - qcom,pmcx0102-rpmh-regulators
- qcom,pmg1110-rpmh-regulators
+ - qcom,pmh0101-rpmh-regulators
+ - qcom,pmh0104-rpmh-regulators
+ - qcom,pmh0110-rpmh-regulators
- qcom,pmi8998-rpmh-regulators
- qcom,pmm8155au-rpmh-regulators
- qcom,pmm8654au-rpmh-regulators
@@ -246,6 +254,7 @@ allOf:
compatible:
enum:
- qcom,pm8005-rpmh-regulators
+ - qcom,pmh0104-rpmh-regulators
then:
patternProperties:
"^vdd-s[1-4]-supply$": true
@@ -422,6 +431,34 @@ allOf:
properties:
vdd-s1-supply: true
+ - if:
+ properties:
+ compatible:
+ enum:
+ - qcom,pmh0101-rpmh-regulators
+ then:
+ properties:
+ vdd-l1-l4-l10-supply: true
+ vdd-l2-l13-l14-supply: true
+ vdd-l3-l11-supply: true
+ vdd-l5-l16-supply: true
+ vdd-l6-l7-supply: true
+ vdd-l8-l9-supply: true
+ patternProperties:
+ "^vdd-l(1[2578])-supply$": true
+ "^vdd-bob[1-2]-supply$": true
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - qcom,pmcx0102-rpmh-regulators
+ - qcom,pmh0110-rpmh-regulators
+ then:
+ patternProperties:
+ "^vdd-l[1-4]-supply$": true
+ "^vdd-s([1-9]|10)-supply$": true
+
- if:
properties:
compatible:
--
2.25.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 2/4] dt-bindings: rpmh-regulator: Update pmic-id property description
2025-09-16 12:58 [PATCH v2 0/4] rpmh-regulators: Update rpmh-regulator driver and dt-bindings for Glymur Kamal Wadhwa
2025-09-16 12:58 ` [PATCH v2 1/4] dt-bindings: rpmh-regulator : Add compatibles for PMH01XX & PMCX0102 Kamal Wadhwa
@ 2025-09-16 12:58 ` Kamal Wadhwa
2025-09-16 15:08 ` Dmitry Baryshkov
2025-09-16 12:58 ` [PATCH v2 3/4] regulator: rpmh-regulator: Add support for new resource name format Kamal Wadhwa
2025-09-16 12:58 ` [PATCH v2 4/4] regulator: rpmh-regulator: Add RPMH regulator support for Glymur Kamal Wadhwa
3 siblings, 1 reply; 7+ messages in thread
From: Kamal Wadhwa @ 2025-09-16 12:58 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, dmitry.baryshkov, konrad.dybcio
Cc: linux-arm-msm, Krzysztof Kozlowski, linux-kernel, devicetree,
Kamal Wadhwa, jishnu.prakash
The `pmic-id` property previously accepted a single lowercase alphabet
in the range [a-n]. However, on new targets such as Glymur, the
property uses a new format: `[A-N]_E[0-3]`, where `[A-N]` represents
the PMIC ID and `[0-3]` represents the BUS ID.
Update the property description to reflect this new pattern format,
matching the updated driver implementation.
Note - Old format [a-n] is still valid and will work for existing
targets.
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
---
Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml b/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml
index 40e57b10ebbebeff130871b6d978df64111b6f29..40ddc64577e78b5c0dbb7b4e8893a08e8b37c92e 100644
--- a/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml
+++ b/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml
@@ -108,7 +108,7 @@ properties:
RPMh resource name suffix used for the regulators found
on this PMIC.
$ref: /schemas/types.yaml#/definitions/string
- enum: [a, b, c, d, e, f, g, h, i, j, k, l, m, n]
+ pattern: "^[a-n]|[A-N]_E[0-3]+$"
qcom,always-wait-for-ack:
description: |
--
2.25.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 3/4] regulator: rpmh-regulator: Add support for new resource name format
2025-09-16 12:58 [PATCH v2 0/4] rpmh-regulators: Update rpmh-regulator driver and dt-bindings for Glymur Kamal Wadhwa
2025-09-16 12:58 ` [PATCH v2 1/4] dt-bindings: rpmh-regulator : Add compatibles for PMH01XX & PMCX0102 Kamal Wadhwa
2025-09-16 12:58 ` [PATCH v2 2/4] dt-bindings: rpmh-regulator: Update pmic-id property description Kamal Wadhwa
@ 2025-09-16 12:58 ` Kamal Wadhwa
2025-09-17 11:05 ` kernel test robot
2025-09-16 12:58 ` [PATCH v2 4/4] regulator: rpmh-regulator: Add RPMH regulator support for Glymur Kamal Wadhwa
3 siblings, 1 reply; 7+ messages in thread
From: Kamal Wadhwa @ 2025-09-16 12:58 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, dmitry.baryshkov, konrad.dybcio
Cc: linux-arm-msm, Krzysztof Kozlowski, linux-kernel, devicetree,
Kamal Wadhwa, jishnu.prakash
Currently rpmh-regulator resource name inside CMD-DB follows this
format: `^(ldo|smp|bob|vs)[a-n][1-9][0-9]?$`
(eg - ldob11, smpa2, bobc1 etc)
Here `[a-n]` in the resource name signifies the `pmic-id`.
However, newer firmware follows a different format that also
includes the `bus_id` as well in the resource name.
New format:
`^(L|S|B)[1-9][0-9]?[A-N]_E[0-3]$`
(eg - L11B_E1, S2A_E0, B1C_E0 etc)
Here `_E[0-3]` at the end is the `bus_id`, and upper case `[A-N]`
is used to denote `pmic-id`, while the regulator `(ldo|smp|bob)`
is replaced with their initials in upper case `(L|S|B|VA)`.
To handle this properly, do the following:
- Remove the `resource_name` member from vreg init data
- Add `index` and `regulator_hw_type` new members, which will
contain the index number and the regulator hardware type
(SMPS/LDO/BOB/VS) which can be combined with the pmic-id read
from the devicetree to generate the resource_name.
- Choose new resource name format if `pmic-id` contains `_E`
in it, else fallback to old format.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
---
drivers/regulator/qcom-rpmh-regulator.c | 1134 ++++++++++++++++---------------
1 file changed, 586 insertions(+), 548 deletions(-)
diff --git a/drivers/regulator/qcom-rpmh-regulator.c b/drivers/regulator/qcom-rpmh-regulator.c
index 109f0aae09b1df431d2e14d45a64d115e87cdec4..525904956705cbb94a5abb63fb050eb967de4109 100644
--- a/drivers/regulator/qcom-rpmh-regulator.c
+++ b/drivers/regulator/qcom-rpmh-regulator.c
@@ -32,6 +32,33 @@ enum rpmh_regulator_type {
XOB,
};
+/**
+ * enum regulator_hw_type - supported regulator types
+ * @SMPS: Switch mode power supply.
+ * @LDO: Linear Dropout regulator.
+ * @BOB: Buck/Boost type regulator.
+ * @VS: Simple voltage ON/OFF switch.
+ */
+enum regulator_hw_type {
+ SMPS,
+ LDO,
+ BOB,
+ VS,
+ NUM_REGULATOR_TYPES,
+};
+
+struct resource_name_formats {
+ const char *rsc_name_fmt;
+ const char *rsc_name_fmt1;
+};
+
+static const struct resource_name_formats vreg_rsc_name_lookup[NUM_REGULATOR_TYPES] = {
+ [SMPS] = {"S%d%s", "smp%s%d"},
+ [LDO] = {"L%d%s", "ldo%s%d"},
+ [BOB] = {"B%d%s", "bob%s%d"},
+ [VS] = {"VS%d%s", "vs%s%d"},
+};
+
#define RPMH_REGULATOR_REG_VRM_VOLTAGE 0x0
#define RPMH_REGULATOR_REG_ENABLE 0x4
#define RPMH_REGULATOR_REG_VRM_MODE 0x8
@@ -64,6 +91,7 @@ enum rpmh_regulator_type {
#define PMIC5_BOB_MODE_AUTO 6
#define PMIC5_BOB_MODE_PWM 7
+#define PMIC_ID_LEN 4
/**
* struct rpmh_vreg_hw_data - RPMh regulator hardware configurations
* @regulator_type: RPMh accelerator type used to manage this
@@ -136,17 +164,17 @@ struct rpmh_vreg {
* struct rpmh_vreg_init_data - initialization data for an RPMh regulator
* @name: Name for the regulator which also corresponds
* to the device tree subnode name of the regulator
- * @resource_name: RPMh regulator resource name format string.
- * This must include exactly one field: '%s' which
- * is filled at run-time with the PMIC ID provided
- * by device tree property qcom,pmic-id. Example:
- * "ldo%s1" for RPMh resource "ldoa1".
+ * @index: This is the index number of the regulator present
+ on the PMIC.
+ * @vreg_hw_type: Regulator HW type enum, this must be BOB, SMPS,
+ * LDO, VS, based on the regulator HW type.
* @supply_name: Parent supply regulator name
* @hw_data: Configuration data for this PMIC regulator type
*/
struct rpmh_vreg_init_data {
const char *name;
- const char *resource_name;
+ enum regulator_hw_type vreg_hw_type;
+ int index;
const char *supply_name;
const struct rpmh_vreg_hw_data *hw_data;
};
@@ -417,6 +445,7 @@ static int rpmh_regulator_init_vreg(struct rpmh_vreg *vreg, struct device *dev,
{
struct regulator_config reg_config = {};
char rpmh_resource_name[20] = "";
+ const char *rsc_name;
const struct rpmh_vreg_init_data *rpmh_data;
struct regulator_init_data *init_data;
struct regulator_dev *rdev;
@@ -433,8 +462,16 @@ static int rpmh_regulator_init_vreg(struct rpmh_vreg *vreg, struct device *dev,
return -EINVAL;
}
- scnprintf(rpmh_resource_name, sizeof(rpmh_resource_name),
- rpmh_data->resource_name, pmic_id);
+ if (strnlen(pmic_id, PMIC_ID_LEN) > 1 && strnstr(pmic_id, "_E", PMIC_ID_LEN)) {
+ rsc_name = vreg_rsc_name_lookup[rpmh_data->vreg_hw_type].rsc_name_fmt;
+ scnprintf(rpmh_resource_name, sizeof(rpmh_resource_name),
+ rsc_name, rpmh_data->index, pmic_id);
+
+ } else {
+ rsc_name = vreg_rsc_name_lookup[rpmh_data->vreg_hw_type].rsc_name_fmt1;
+ scnprintf(rpmh_resource_name, sizeof(rpmh_resource_name),
+ rsc_name, pmic_id, rpmh_data->index);
+ }
vreg->addr = cmd_db_read_addr(rpmh_resource_name);
if (!vreg->addr) {
@@ -904,671 +941,672 @@ static const struct rpmh_vreg_hw_data pmic5_bob = {
.of_map_mode = rpmh_regulator_pmic4_bob_of_map_mode,
};
-#define RPMH_VREG(_name, _resource_name, _hw_data, _supply_name) \
+#define RPMH_VREG(_name, _vreg_hw_type, _index, _hw_data, _supply_name) \
{ \
.name = _name, \
- .resource_name = _resource_name, \
+ .vreg_hw_type = _vreg_hw_type, \
+ .index = _index, \
.hw_data = _hw_data, \
.supply_name = _supply_name, \
}
static const struct rpmh_vreg_init_data pm8998_vreg_data[] = {
- RPMH_VREG("smps1", "smp%s1", &pmic4_ftsmps426, "vdd-s1"),
- RPMH_VREG("smps2", "smp%s2", &pmic4_ftsmps426, "vdd-s2"),
- RPMH_VREG("smps3", "smp%s3", &pmic4_hfsmps3, "vdd-s3"),
- RPMH_VREG("smps4", "smp%s4", &pmic4_hfsmps3, "vdd-s4"),
- RPMH_VREG("smps5", "smp%s5", &pmic4_hfsmps3, "vdd-s5"),
- RPMH_VREG("smps6", "smp%s6", &pmic4_ftsmps426, "vdd-s6"),
- RPMH_VREG("smps7", "smp%s7", &pmic4_ftsmps426, "vdd-s7"),
- RPMH_VREG("smps8", "smp%s8", &pmic4_ftsmps426, "vdd-s8"),
- RPMH_VREG("smps9", "smp%s9", &pmic4_ftsmps426, "vdd-s9"),
- RPMH_VREG("smps10", "smp%s10", &pmic4_ftsmps426, "vdd-s10"),
- RPMH_VREG("smps11", "smp%s11", &pmic4_ftsmps426, "vdd-s11"),
- RPMH_VREG("smps12", "smp%s12", &pmic4_ftsmps426, "vdd-s12"),
- RPMH_VREG("smps13", "smp%s13", &pmic4_ftsmps426, "vdd-s13"),
- RPMH_VREG("ldo1", "ldo%s1", &pmic4_nldo, "vdd-l1-l27"),
- RPMH_VREG("ldo2", "ldo%s2", &pmic4_nldo, "vdd-l2-l8-l17"),
- RPMH_VREG("ldo3", "ldo%s3", &pmic4_nldo, "vdd-l3-l11"),
- RPMH_VREG("ldo4", "ldo%s4", &pmic4_nldo, "vdd-l4-l5"),
- RPMH_VREG("ldo5", "ldo%s5", &pmic4_nldo, "vdd-l4-l5"),
- RPMH_VREG("ldo6", "ldo%s6", &pmic4_pldo, "vdd-l6"),
- RPMH_VREG("ldo7", "ldo%s7", &pmic4_pldo_lv, "vdd-l7-l12-l14-l15"),
- RPMH_VREG("ldo8", "ldo%s8", &pmic4_nldo, "vdd-l2-l8-l17"),
- RPMH_VREG("ldo9", "ldo%s9", &pmic4_pldo, "vdd-l9"),
- RPMH_VREG("ldo10", "ldo%s10", &pmic4_pldo, "vdd-l10-l23-l25"),
- RPMH_VREG("ldo11", "ldo%s11", &pmic4_nldo, "vdd-l3-l11"),
- RPMH_VREG("ldo12", "ldo%s12", &pmic4_pldo_lv, "vdd-l7-l12-l14-l15"),
- RPMH_VREG("ldo13", "ldo%s13", &pmic4_pldo, "vdd-l13-l19-l21"),
- RPMH_VREG("ldo14", "ldo%s14", &pmic4_pldo_lv, "vdd-l7-l12-l14-l15"),
- RPMH_VREG("ldo15", "ldo%s15", &pmic4_pldo_lv, "vdd-l7-l12-l14-l15"),
- RPMH_VREG("ldo16", "ldo%s16", &pmic4_pldo, "vdd-l16-l28"),
- RPMH_VREG("ldo17", "ldo%s17", &pmic4_nldo, "vdd-l2-l8-l17"),
- RPMH_VREG("ldo18", "ldo%s18", &pmic4_pldo, "vdd-l18-l22"),
- RPMH_VREG("ldo19", "ldo%s19", &pmic4_pldo, "vdd-l13-l19-l21"),
- RPMH_VREG("ldo20", "ldo%s20", &pmic4_pldo, "vdd-l20-l24"),
- RPMH_VREG("ldo21", "ldo%s21", &pmic4_pldo, "vdd-l13-l19-l21"),
- RPMH_VREG("ldo22", "ldo%s22", &pmic4_pldo, "vdd-l18-l22"),
- RPMH_VREG("ldo23", "ldo%s23", &pmic4_pldo, "vdd-l10-l23-l25"),
- RPMH_VREG("ldo24", "ldo%s24", &pmic4_pldo, "vdd-l20-l24"),
- RPMH_VREG("ldo25", "ldo%s25", &pmic4_pldo, "vdd-l10-l23-l25"),
- RPMH_VREG("ldo26", "ldo%s26", &pmic4_nldo, "vdd-l26"),
- RPMH_VREG("ldo27", "ldo%s27", &pmic4_nldo, "vdd-l1-l27"),
- RPMH_VREG("ldo28", "ldo%s28", &pmic4_pldo, "vdd-l16-l28"),
- RPMH_VREG("lvs1", "vs%s1", &pmic4_lvs, "vin-lvs-1-2"),
- RPMH_VREG("lvs2", "vs%s2", &pmic4_lvs, "vin-lvs-1-2"),
+ RPMH_VREG("smps1", SMPS, 1, &pmic4_ftsmps426, "vdd-s1"),
+ RPMH_VREG("smps2", SMPS, 2, &pmic4_ftsmps426, "vdd-s2"),
+ RPMH_VREG("smps3", SMPS, 3, &pmic4_hfsmps3, "vdd-s3"),
+ RPMH_VREG("smps4", SMPS, 4, &pmic4_hfsmps3, "vdd-s4"),
+ RPMH_VREG("smps5", SMPS, 5, &pmic4_hfsmps3, "vdd-s5"),
+ RPMH_VREG("smps6", SMPS, 6, &pmic4_ftsmps426, "vdd-s6"),
+ RPMH_VREG("smps7", SMPS, 7, &pmic4_ftsmps426, "vdd-s7"),
+ RPMH_VREG("smps8", SMPS, 8, &pmic4_ftsmps426, "vdd-s8"),
+ RPMH_VREG("smps9", SMPS, 9, &pmic4_ftsmps426, "vdd-s9"),
+ RPMH_VREG("smps10", SMPS, 10, &pmic4_ftsmps426, "vdd-s10"),
+ RPMH_VREG("smps11", SMPS, 11, &pmic4_ftsmps426, "vdd-s11"),
+ RPMH_VREG("smps12", SMPS, 12, &pmic4_ftsmps426, "vdd-s12"),
+ RPMH_VREG("smps13", SMPS, 13, &pmic4_ftsmps426, "vdd-s13"),
+ RPMH_VREG("ldo1", LDO, 1, &pmic4_nldo, "vdd-l1-l27"),
+ RPMH_VREG("ldo2", LDO, 2, &pmic4_nldo, "vdd-l2-l8-l17"),
+ RPMH_VREG("ldo3", LDO, 3, &pmic4_nldo, "vdd-l3-l11"),
+ RPMH_VREG("ldo4", LDO, 4, &pmic4_nldo, "vdd-l4-l5"),
+ RPMH_VREG("ldo5", LDO, 5, &pmic4_nldo, "vdd-l4-l5"),
+ RPMH_VREG("ldo6", LDO, 6, &pmic4_pldo, "vdd-l6"),
+ RPMH_VREG("ldo7", LDO, 7, &pmic4_pldo_lv, "vdd-l7-l12-l14-l15"),
+ RPMH_VREG("ldo8", LDO, 8, &pmic4_nldo, "vdd-l2-l8-l17"),
+ RPMH_VREG("ldo9", LDO, 9, &pmic4_pldo, "vdd-l9"),
+ RPMH_VREG("ldo10", LDO, 10, &pmic4_pldo, "vdd-l10-l23-l25"),
+ RPMH_VREG("ldo11", LDO, 11, &pmic4_nldo, "vdd-l3-l11"),
+ RPMH_VREG("ldo12", LDO, 12, &pmic4_pldo_lv, "vdd-l7-l12-l14-l15"),
+ RPMH_VREG("ldo13", LDO, 13, &pmic4_pldo, "vdd-l13-l19-l21"),
+ RPMH_VREG("ldo14", LDO, 14, &pmic4_pldo_lv, "vdd-l7-l12-l14-l15"),
+ RPMH_VREG("ldo15", LDO, 15, &pmic4_pldo_lv, "vdd-l7-l12-l14-l15"),
+ RPMH_VREG("ldo16", LDO, 16, &pmic4_pldo, "vdd-l16-l28"),
+ RPMH_VREG("ldo17", LDO, 17, &pmic4_nldo, "vdd-l2-l8-l17"),
+ RPMH_VREG("ldo18", LDO, 18, &pmic4_pldo, "vdd-l18-l22"),
+ RPMH_VREG("ldo19", LDO, 19, &pmic4_pldo, "vdd-l13-l19-l21"),
+ RPMH_VREG("ldo20", LDO, 20, &pmic4_pldo, "vdd-l20-l24"),
+ RPMH_VREG("ldo21", LDO, 21, &pmic4_pldo, "vdd-l13-l19-l21"),
+ RPMH_VREG("ldo22", LDO, 22, &pmic4_pldo, "vdd-l18-l22"),
+ RPMH_VREG("ldo23", LDO, 23, &pmic4_pldo, "vdd-l10-l23-l25"),
+ RPMH_VREG("ldo24", LDO, 24, &pmic4_pldo, "vdd-l20-l24"),
+ RPMH_VREG("ldo25", LDO, 25, &pmic4_pldo, "vdd-l10-l23-l25"),
+ RPMH_VREG("ldo26", LDO, 26, &pmic4_nldo, "vdd-l26"),
+ RPMH_VREG("ldo27", LDO, 27, &pmic4_nldo, "vdd-l1-l27"),
+ RPMH_VREG("ldo28", LDO, 28, &pmic4_pldo, "vdd-l16-l28"),
+ RPMH_VREG("lvs1", VS, 1, &pmic4_lvs, "vin-lvs-1-2"),
+ RPMH_VREG("lvs2", VS, 2, &pmic4_lvs, "vin-lvs-1-2"),
{}
};
static const struct rpmh_vreg_init_data pmg1110_vreg_data[] = {
- RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps510, "vdd-s1"),
+ RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps510, "vdd-s1"),
{}
};
static const struct rpmh_vreg_init_data pmi8998_vreg_data[] = {
- RPMH_VREG("bob", "bob%s1", &pmic4_bob, "vdd-bob"),
+ RPMH_VREG("bob", BOB, 1, &pmic4_bob, "vdd-bob"),
{}
};
static const struct rpmh_vreg_init_data pm8005_vreg_data[] = {
- RPMH_VREG("smps1", "smp%s1", &pmic4_ftsmps426, "vdd-s1"),
- RPMH_VREG("smps2", "smp%s2", &pmic4_ftsmps426, "vdd-s2"),
- RPMH_VREG("smps3", "smp%s3", &pmic4_ftsmps426, "vdd-s3"),
- RPMH_VREG("smps4", "smp%s4", &pmic4_ftsmps426, "vdd-s4"),
+ RPMH_VREG("smps1", SMPS, 1, &pmic4_ftsmps426, "vdd-s1"),
+ RPMH_VREG("smps2", SMPS, 2, &pmic4_ftsmps426, "vdd-s2"),
+ RPMH_VREG("smps3", SMPS, 3, &pmic4_ftsmps426, "vdd-s3"),
+ RPMH_VREG("smps4", SMPS, 4, &pmic4_ftsmps426, "vdd-s4"),
{}
};
static const struct rpmh_vreg_init_data pm8150_vreg_data[] = {
- RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps510, "vdd-s1"),
- RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps510, "vdd-s2"),
- RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps510, "vdd-s3"),
- RPMH_VREG("smps4", "smp%s4", &pmic5_hfsmps510, "vdd-s4"),
- RPMH_VREG("smps5", "smp%s5", &pmic5_hfsmps510, "vdd-s5"),
- RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps510, "vdd-s6"),
- RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps510, "vdd-s7"),
- RPMH_VREG("smps8", "smp%s8", &pmic5_ftsmps510, "vdd-s8"),
- RPMH_VREG("smps9", "smp%s9", &pmic5_ftsmps510, "vdd-s9"),
- RPMH_VREG("smps10", "smp%s10", &pmic5_ftsmps510, "vdd-s10"),
- RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo, "vdd-l1-l8-l11"),
- RPMH_VREG("ldo2", "ldo%s2", &pmic5_pldo, "vdd-l2-l10"),
- RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l3-l4-l5-l18"),
- RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo, "vdd-l3-l4-l5-l18"),
- RPMH_VREG("ldo5", "ldo%s5", &pmic5_nldo, "vdd-l3-l4-l5-l18"),
- RPMH_VREG("ldo6", "ldo%s6", &pmic5_nldo, "vdd-l6-l9"),
- RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo, "vdd-l7-l12-l14-l15"),
- RPMH_VREG("ldo8", "ldo%s8", &pmic5_nldo, "vdd-l1-l8-l11"),
- RPMH_VREG("ldo9", "ldo%s9", &pmic5_nldo, "vdd-l6-l9"),
- RPMH_VREG("ldo10", "ldo%s10", &pmic5_pldo, "vdd-l2-l10"),
- RPMH_VREG("ldo11", "ldo%s11", &pmic5_nldo, "vdd-l1-l8-l11"),
- RPMH_VREG("ldo12", "ldo%s12", &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"),
- RPMH_VREG("ldo13", "ldo%s13", &pmic5_pldo, "vdd-l13-l16-l17"),
- RPMH_VREG("ldo14", "ldo%s14", &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"),
- RPMH_VREG("ldo15", "ldo%s15", &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"),
- RPMH_VREG("ldo16", "ldo%s16", &pmic5_pldo, "vdd-l13-l16-l17"),
- RPMH_VREG("ldo17", "ldo%s17", &pmic5_pldo, "vdd-l13-l16-l17"),
- RPMH_VREG("ldo18", "ldo%s18", &pmic5_nldo, "vdd-l3-l4-l5-l18"),
+ RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps510, "vdd-s1"),
+ RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps510, "vdd-s2"),
+ RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps510, "vdd-s3"),
+ RPMH_VREG("smps4", SMPS, 4, &pmic5_hfsmps510, "vdd-s4"),
+ RPMH_VREG("smps5", SMPS, 5, &pmic5_hfsmps510, "vdd-s5"),
+ RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps510, "vdd-s6"),
+ RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps510, "vdd-s7"),
+ RPMH_VREG("smps8", SMPS, 8, &pmic5_ftsmps510, "vdd-s8"),
+ RPMH_VREG("smps9", SMPS, 9, &pmic5_ftsmps510, "vdd-s9"),
+ RPMH_VREG("smps10", SMPS, 10, &pmic5_ftsmps510, "vdd-s10"),
+ RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1-l8-l11"),
+ RPMH_VREG("ldo2", LDO, 2, &pmic5_pldo, "vdd-l2-l10"),
+ RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3-l4-l5-l18"),
+ RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo, "vdd-l3-l4-l5-l18"),
+ RPMH_VREG("ldo5", LDO, 5, &pmic5_nldo, "vdd-l3-l4-l5-l18"),
+ RPMH_VREG("ldo6", LDO, 6, &pmic5_nldo, "vdd-l6-l9"),
+ RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo, "vdd-l7-l12-l14-l15"),
+ RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo, "vdd-l1-l8-l11"),
+ RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo, "vdd-l6-l9"),
+ RPMH_VREG("ldo10", LDO, 10, &pmic5_pldo, "vdd-l2-l10"),
+ RPMH_VREG("ldo11", LDO, 11, &pmic5_nldo, "vdd-l1-l8-l11"),
+ RPMH_VREG("ldo12", LDO, 12, &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"),
+ RPMH_VREG("ldo13", LDO, 13, &pmic5_pldo, "vdd-l13-l16-l17"),
+ RPMH_VREG("ldo14", LDO, 14, &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"),
+ RPMH_VREG("ldo15", LDO, 15, &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"),
+ RPMH_VREG("ldo16", LDO, 16, &pmic5_pldo, "vdd-l13-l16-l17"),
+ RPMH_VREG("ldo17", LDO, 17, &pmic5_pldo, "vdd-l13-l16-l17"),
+ RPMH_VREG("ldo18", LDO, 18, &pmic5_nldo, "vdd-l3-l4-l5-l18"),
{}
};
static const struct rpmh_vreg_init_data pm8150l_vreg_data[] = {
- RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps510, "vdd-s1"),
- RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps510, "vdd-s2"),
- RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps510, "vdd-s3"),
- RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps510, "vdd-s4"),
- RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps510, "vdd-s5"),
- RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps510, "vdd-s6"),
- RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps510, "vdd-s7"),
- RPMH_VREG("smps8", "smp%s8", &pmic5_hfsmps510, "vdd-s8"),
- RPMH_VREG("ldo1", "ldo%s1", &pmic5_pldo_lv, "vdd-l1-l8"),
- RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo, "vdd-l2-l3"),
- RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l2-l3"),
- RPMH_VREG("ldo4", "ldo%s4", &pmic5_pldo, "vdd-l4-l5-l6"),
- RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo, "vdd-l4-l5-l6"),
- RPMH_VREG("ldo6", "ldo%s6", &pmic5_pldo, "vdd-l4-l5-l6"),
- RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo, "vdd-l7-l11"),
- RPMH_VREG("ldo8", "ldo%s8", &pmic5_pldo_lv, "vdd-l1-l8"),
- RPMH_VREG("ldo9", "ldo%s9", &pmic5_pldo, "vdd-l9-l10"),
- RPMH_VREG("ldo10", "ldo%s10", &pmic5_pldo, "vdd-l9-l10"),
- RPMH_VREG("ldo11", "ldo%s11", &pmic5_pldo, "vdd-l7-l11"),
- RPMH_VREG("bob", "bob%s1", &pmic5_bob, "vdd-bob"),
+ RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps510, "vdd-s1"),
+ RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps510, "vdd-s2"),
+ RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps510, "vdd-s3"),
+ RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps510, "vdd-s4"),
+ RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps510, "vdd-s5"),
+ RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps510, "vdd-s6"),
+ RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps510, "vdd-s7"),
+ RPMH_VREG("smps8", SMPS, 8, &pmic5_hfsmps510, "vdd-s8"),
+ RPMH_VREG("ldo1", LDO, 1, &pmic5_pldo_lv, "vdd-l1-l8"),
+ RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo, "vdd-l2-l3"),
+ RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l2-l3"),
+ RPMH_VREG("ldo4", LDO, 4, &pmic5_pldo, "vdd-l4-l5-l6"),
+ RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo, "vdd-l4-l5-l6"),
+ RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo, "vdd-l4-l5-l6"),
+ RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo, "vdd-l7-l11"),
+ RPMH_VREG("ldo8", LDO, 8, &pmic5_pldo_lv, "vdd-l1-l8"),
+ RPMH_VREG("ldo9", LDO, 9, &pmic5_pldo, "vdd-l9-l10"),
+ RPMH_VREG("ldo10", LDO, 10, &pmic5_pldo, "vdd-l9-l10"),
+ RPMH_VREG("ldo11", LDO, 11, &pmic5_pldo, "vdd-l7-l11"),
+ RPMH_VREG("bob", BOB, 1, &pmic5_bob, "vdd-bob"),
{}
};
static const struct rpmh_vreg_init_data pmm8155au_vreg_data[] = {
- RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps510, "vdd-s1"),
- RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps510, "vdd-s2"),
- RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps510, "vdd-s3"),
- RPMH_VREG("smps4", "smp%s4", &pmic5_hfsmps510, "vdd-s4"),
- RPMH_VREG("smps5", "smp%s5", &pmic5_hfsmps510, "vdd-s5"),
- RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps510, "vdd-s6"),
- RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps510, "vdd-s7"),
- RPMH_VREG("smps8", "smp%s8", &pmic5_ftsmps510, "vdd-s8"),
- RPMH_VREG("smps9", "smp%s9", &pmic5_ftsmps510, "vdd-s9"),
- RPMH_VREG("smps10", "smp%s10", &pmic5_ftsmps510, "vdd-s10"),
- RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo, "vdd-l1-l8-l11"),
- RPMH_VREG("ldo2", "ldo%s2", &pmic5_pldo, "vdd-l2-l10"),
- RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l3-l4-l5-l18"),
- RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo, "vdd-l3-l4-l5-l18"),
- RPMH_VREG("ldo5", "ldo%s5", &pmic5_nldo, "vdd-l3-l4-l5-l18"),
- RPMH_VREG("ldo6", "ldo%s6", &pmic5_nldo, "vdd-l6-l9"),
- RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"),
- RPMH_VREG("ldo8", "ldo%s8", &pmic5_nldo, "vdd-l1-l8-l11"),
- RPMH_VREG("ldo9", "ldo%s9", &pmic5_nldo, "vdd-l6-l9"),
- RPMH_VREG("ldo10", "ldo%s10", &pmic5_pldo, "vdd-l2-l10"),
- RPMH_VREG("ldo11", "ldo%s11", &pmic5_nldo, "vdd-l1-l8-l11"),
- RPMH_VREG("ldo12", "ldo%s12", &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"),
- RPMH_VREG("ldo13", "ldo%s13", &pmic5_pldo, "vdd-l13-l16-l17"),
- RPMH_VREG("ldo14", "ldo%s14", &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"),
- RPMH_VREG("ldo15", "ldo%s15", &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"),
- RPMH_VREG("ldo16", "ldo%s16", &pmic5_pldo, "vdd-l13-l16-l17"),
- RPMH_VREG("ldo17", "ldo%s17", &pmic5_pldo, "vdd-l13-l16-l17"),
- RPMH_VREG("ldo18", "ldo%s18", &pmic5_nldo, "vdd-l3-l4-l5-l18"),
+ RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps510, "vdd-s1"),
+ RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps510, "vdd-s2"),
+ RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps510, "vdd-s3"),
+ RPMH_VREG("smps4", SMPS, 4, &pmic5_hfsmps510, "vdd-s4"),
+ RPMH_VREG("smps5", SMPS, 5, &pmic5_hfsmps510, "vdd-s5"),
+ RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps510, "vdd-s6"),
+ RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps510, "vdd-s7"),
+ RPMH_VREG("smps8", SMPS, 8, &pmic5_ftsmps510, "vdd-s8"),
+ RPMH_VREG("smps9", SMPS, 9, &pmic5_ftsmps510, "vdd-s9"),
+ RPMH_VREG("smps10", SMPS, 10, &pmic5_ftsmps510, "vdd-s10"),
+ RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1-l8-l11"),
+ RPMH_VREG("ldo2", LDO, 2, &pmic5_pldo, "vdd-l2-l10"),
+ RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3-l4-l5-l18"),
+ RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo, "vdd-l3-l4-l5-l18"),
+ RPMH_VREG("ldo5", LDO, 5, &pmic5_nldo, "vdd-l3-l4-l5-l18"),
+ RPMH_VREG("ldo6", LDO, 6, &pmic5_nldo, "vdd-l6-l9"),
+ RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"),
+ RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo, "vdd-l1-l8-l11"),
+ RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo, "vdd-l6-l9"),
+ RPMH_VREG("ldo10", LDO, 10, &pmic5_pldo, "vdd-l2-l10"),
+ RPMH_VREG("ldo11", LDO, 11, &pmic5_nldo, "vdd-l1-l8-l11"),
+ RPMH_VREG("ldo12", LDO, 12, &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"),
+ RPMH_VREG("ldo13", LDO, 13, &pmic5_pldo, "vdd-l13-l16-l17"),
+ RPMH_VREG("ldo14", LDO, 14, &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"),
+ RPMH_VREG("ldo15", LDO, 15, &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"),
+ RPMH_VREG("ldo16", LDO, 16, &pmic5_pldo, "vdd-l13-l16-l17"),
+ RPMH_VREG("ldo17", LDO, 17, &pmic5_pldo, "vdd-l13-l16-l17"),
+ RPMH_VREG("ldo18", LDO, 18, &pmic5_nldo, "vdd-l3-l4-l5-l18"),
{}
};
static const struct rpmh_vreg_init_data pmm8654au_vreg_data[] = {
- RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps527, "vdd-s1"),
- RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps527, "vdd-s2"),
- RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps527, "vdd-s3"),
- RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps527, "vdd-s4"),
- RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps527, "vdd-s5"),
- RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps527, "vdd-s6"),
- RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps527, "vdd-s7"),
- RPMH_VREG("smps8", "smp%s8", &pmic5_ftsmps527, "vdd-s8"),
- RPMH_VREG("smps9", "smp%s9", &pmic5_ftsmps527, "vdd-s9"),
- RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-s9"),
- RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo515, "vdd-l2-l3"),
- RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l2-l3"),
- RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo515, "vdd-s9"),
- RPMH_VREG("ldo5", "ldo%s5", &pmic5_nldo515, "vdd-s9"),
- RPMH_VREG("ldo6", "ldo%s6", &pmic5_nldo515, "vdd-l6-l7"),
- RPMH_VREG("ldo7", "ldo%s7", &pmic5_nldo515, "vdd-l6-l7"),
- RPMH_VREG("ldo8", "ldo%s8", &pmic5_pldo515_mv, "vdd-l8-l9"),
- RPMH_VREG("ldo9", "ldo%s9", &pmic5_pldo, "vdd-l8-l9"),
+ RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps527, "vdd-s1"),
+ RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps527, "vdd-s2"),
+ RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps527, "vdd-s3"),
+ RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps527, "vdd-s4"),
+ RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps527, "vdd-s5"),
+ RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps527, "vdd-s6"),
+ RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps527, "vdd-s7"),
+ RPMH_VREG("smps8", SMPS, 8, &pmic5_ftsmps527, "vdd-s8"),
+ RPMH_VREG("smps9", SMPS, 9, &pmic5_ftsmps527, "vdd-s9"),
+ RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo515, "vdd-s9"),
+ RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo515, "vdd-l2-l3"),
+ RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo515, "vdd-l2-l3"),
+ RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo515, "vdd-s9"),
+ RPMH_VREG("ldo5", LDO, 5, &pmic5_nldo515, "vdd-s9"),
+ RPMH_VREG("ldo6", LDO, 6, &pmic5_nldo515, "vdd-l6-l7"),
+ RPMH_VREG("ldo7", LDO, 7, &pmic5_nldo515, "vdd-l6-l7"),
+ RPMH_VREG("ldo8", LDO, 8, &pmic5_pldo515_mv, "vdd-l8-l9"),
+ RPMH_VREG("ldo9", LDO, 9, &pmic5_pldo, "vdd-l8-l9"),
{}
};
static const struct rpmh_vreg_init_data pm8350_vreg_data[] = {
- RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps510, "vdd-s1"),
- RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps510, "vdd-s2"),
- RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps510, "vdd-s3"),
- RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps510, "vdd-s4"),
- RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps510, "vdd-s5"),
- RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps510, "vdd-s6"),
- RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps510, "vdd-s7"),
- RPMH_VREG("smps8", "smp%s8", &pmic5_ftsmps510, "vdd-s8"),
- RPMH_VREG("smps9", "smp%s9", &pmic5_ftsmps510, "vdd-s9"),
- RPMH_VREG("smps10", "smp%s10", &pmic5_hfsmps510, "vdd-s10"),
- RPMH_VREG("smps11", "smp%s11", &pmic5_hfsmps510, "vdd-s11"),
- RPMH_VREG("smps12", "smp%s12", &pmic5_hfsmps510, "vdd-s12"),
- RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo, "vdd-l1-l4"),
- RPMH_VREG("ldo2", "ldo%s2", &pmic5_pldo, "vdd-l2-l7"),
- RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l3-l5"),
- RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo, "vdd-l1-l4"),
- RPMH_VREG("ldo5", "ldo%s5", &pmic5_nldo, "vdd-l3-l5"),
- RPMH_VREG("ldo6", "ldo%s6", &pmic5_nldo, "vdd-l6-l9-l10"),
- RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo, "vdd-l2-l7"),
- RPMH_VREG("ldo8", "ldo%s8", &pmic5_nldo, "vdd-l8"),
- RPMH_VREG("ldo9", "ldo%s9", &pmic5_nldo, "vdd-l6-l9-l10"),
- RPMH_VREG("ldo10", "ldo%s10", &pmic5_nldo, "vdd-l6-l9-l10"),
+ RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps510, "vdd-s1"),
+ RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps510, "vdd-s2"),
+ RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps510, "vdd-s3"),
+ RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps510, "vdd-s4"),
+ RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps510, "vdd-s5"),
+ RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps510, "vdd-s6"),
+ RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps510, "vdd-s7"),
+ RPMH_VREG("smps8", SMPS, 8, &pmic5_ftsmps510, "vdd-s8"),
+ RPMH_VREG("smps9", SMPS, 9, &pmic5_ftsmps510, "vdd-s9"),
+ RPMH_VREG("smps10", SMPS, 10, &pmic5_hfsmps510, "vdd-s10"),
+ RPMH_VREG("smps11", SMPS, 11, &pmic5_hfsmps510, "vdd-s11"),
+ RPMH_VREG("smps12", SMPS, 12, &pmic5_hfsmps510, "vdd-s12"),
+ RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1-l4"),
+ RPMH_VREG("ldo2", LDO, 2, &pmic5_pldo, "vdd-l2-l7"),
+ RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3-l5"),
+ RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo, "vdd-l1-l4"),
+ RPMH_VREG("ldo5", LDO, 5, &pmic5_nldo, "vdd-l3-l5"),
+ RPMH_VREG("ldo6", LDO, 6, &pmic5_nldo, "vdd-l6-l9-l10"),
+ RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo, "vdd-l2-l7"),
+ RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo, "vdd-l8"),
+ RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo, "vdd-l6-l9-l10"),
+ RPMH_VREG("ldo10", LDO, 10, &pmic5_nldo, "vdd-l6-l9-l10"),
{}
};
static const struct rpmh_vreg_init_data pm8350c_vreg_data[] = {
- RPMH_VREG("smps1", "smp%s1", &pmic5_hfsmps515, "vdd-s1"),
- RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps510, "vdd-s2"),
- RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps510, "vdd-s3"),
- RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps510, "vdd-s4"),
- RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps510, "vdd-s5"),
- RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps510, "vdd-s6"),
- RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps510, "vdd-s7"),
- RPMH_VREG("smps8", "smp%s8", &pmic5_ftsmps510, "vdd-s8"),
- RPMH_VREG("smps9", "smp%s9", &pmic5_ftsmps510, "vdd-s9"),
- RPMH_VREG("smps10", "smp%s10", &pmic5_ftsmps510, "vdd-s10"),
- RPMH_VREG("ldo1", "ldo%s1", &pmic5_pldo_lv, "vdd-l1-l12"),
- RPMH_VREG("ldo2", "ldo%s2", &pmic5_pldo_lv, "vdd-l2-l8"),
- RPMH_VREG("ldo3", "ldo%s3", &pmic5_pldo, "vdd-l3-l4-l5-l7-l13"),
- RPMH_VREG("ldo4", "ldo%s4", &pmic5_pldo, "vdd-l3-l4-l5-l7-l13"),
- RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo, "vdd-l3-l4-l5-l7-l13"),
- RPMH_VREG("ldo6", "ldo%s6", &pmic5_pldo, "vdd-l6-l9-l11"),
- RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo, "vdd-l3-l4-l5-l7-l13"),
- RPMH_VREG("ldo8", "ldo%s8", &pmic5_pldo_lv, "vdd-l2-l8"),
- RPMH_VREG("ldo9", "ldo%s9", &pmic5_pldo, "vdd-l6-l9-l11"),
- RPMH_VREG("ldo10", "ldo%s10", &pmic5_nldo, "vdd-l10"),
- RPMH_VREG("ldo11", "ldo%s11", &pmic5_pldo, "vdd-l6-l9-l11"),
- RPMH_VREG("ldo12", "ldo%s12", &pmic5_pldo_lv, "vdd-l1-l12"),
- RPMH_VREG("ldo13", "ldo%s13", &pmic5_pldo, "vdd-l3-l4-l5-l7-l13"),
- RPMH_VREG("bob", "bob%s1", &pmic5_bob, "vdd-bob"),
+ RPMH_VREG("smps1", SMPS, 1, &pmic5_hfsmps515, "vdd-s1"),
+ RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps510, "vdd-s2"),
+ RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps510, "vdd-s3"),
+ RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps510, "vdd-s4"),
+ RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps510, "vdd-s5"),
+ RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps510, "vdd-s6"),
+ RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps510, "vdd-s7"),
+ RPMH_VREG("smps8", SMPS, 8, &pmic5_ftsmps510, "vdd-s8"),
+ RPMH_VREG("smps9", SMPS, 9, &pmic5_ftsmps510, "vdd-s9"),
+ RPMH_VREG("smps10", SMPS, 10, &pmic5_ftsmps510, "vdd-s10"),
+ RPMH_VREG("ldo1", LDO, 1, &pmic5_pldo_lv, "vdd-l1-l12"),
+ RPMH_VREG("ldo2", LDO, 2, &pmic5_pldo_lv, "vdd-l2-l8"),
+ RPMH_VREG("ldo3", LDO, 3, &pmic5_pldo, "vdd-l3-l4-l5-l7-l13"),
+ RPMH_VREG("ldo4", LDO, 4, &pmic5_pldo, "vdd-l3-l4-l5-l7-l13"),
+ RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo, "vdd-l3-l4-l5-l7-l13"),
+ RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo, "vdd-l6-l9-l11"),
+ RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo, "vdd-l3-l4-l5-l7-l13"),
+ RPMH_VREG("ldo8", LDO, 8, &pmic5_pldo_lv, "vdd-l2-l8"),
+ RPMH_VREG("ldo9", LDO, 9, &pmic5_pldo, "vdd-l6-l9-l11"),
+ RPMH_VREG("ldo10", LDO, 10, &pmic5_nldo, "vdd-l10"),
+ RPMH_VREG("ldo11", LDO, 11, &pmic5_pldo, "vdd-l6-l9-l11"),
+ RPMH_VREG("ldo12", LDO, 12, &pmic5_pldo_lv, "vdd-l1-l12"),
+ RPMH_VREG("ldo13", LDO, 13, &pmic5_pldo, "vdd-l3-l4-l5-l7-l13"),
+ RPMH_VREG("bob", BOB, 1, &pmic5_bob, "vdd-bob"),
{}
};
static const struct rpmh_vreg_init_data pm8450_vreg_data[] = {
- RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps520, "vdd-s1"),
- RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps520, "vdd-s2"),
- RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps520, "vdd-s3"),
- RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps520, "vdd-s4"),
- RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps520, "vdd-s5"),
- RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps520, "vdd-s6"),
- RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo, "vdd-l1"),
- RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo, "vdd-l2"),
- RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l3"),
- RPMH_VREG("ldo4", "ldo%s4", &pmic5_pldo_lv, "vdd-l4"),
+ RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps520, "vdd-s1"),
+ RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps520, "vdd-s2"),
+ RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps520, "vdd-s3"),
+ RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps520, "vdd-s4"),
+ RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps520, "vdd-s5"),
+ RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps520, "vdd-s6"),
+ RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1"),
+ RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo, "vdd-l2"),
+ RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3"),
+ RPMH_VREG("ldo4", LDO, 4, &pmic5_pldo_lv, "vdd-l4"),
{}
};
static const struct rpmh_vreg_init_data pm8550_vreg_data[] = {
- RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-l1-l4-l10"),
- RPMH_VREG("ldo2", "ldo%s2", &pmic5_pldo, "vdd-l2-l13-l14"),
- RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l3"),
- RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo515, "vdd-l1-l4-l10"),
- RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo, "vdd-l5-l16"),
- RPMH_VREG("ldo6", "ldo%s6", &pmic5_pldo, "vdd-l6-l7"),
- RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo, "vdd-l6-l7"),
- RPMH_VREG("ldo8", "ldo%s8", &pmic5_pldo, "vdd-l8-l9"),
- RPMH_VREG("ldo9", "ldo%s9", &pmic5_pldo, "vdd-l8-l9"),
- RPMH_VREG("ldo10", "ldo%s10", &pmic5_nldo515, "vdd-l1-l4-l10"),
- RPMH_VREG("ldo11", "ldo%s11", &pmic5_nldo515, "vdd-l11"),
- RPMH_VREG("ldo12", "ldo%s12", &pmic5_nldo515, "vdd-l12"),
- RPMH_VREG("ldo13", "ldo%s13", &pmic5_pldo, "vdd-l2-l13-l14"),
- RPMH_VREG("ldo14", "ldo%s14", &pmic5_pldo, "vdd-l2-l13-l14"),
- RPMH_VREG("ldo15", "ldo%s15", &pmic5_nldo515, "vdd-l15"),
- RPMH_VREG("ldo16", "ldo%s16", &pmic5_pldo, "vdd-l5-l16"),
- RPMH_VREG("ldo17", "ldo%s17", &pmic5_pldo, "vdd-l17"),
- RPMH_VREG("bob1", "bob%s1", &pmic5_bob, "vdd-bob1"),
- RPMH_VREG("bob2", "bob%s2", &pmic5_bob, "vdd-bob2"),
+ RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo515, "vdd-l1-l4-l10"),
+ RPMH_VREG("ldo2", LDO, 2, &pmic5_pldo, "vdd-l2-l13-l14"),
+ RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo515, "vdd-l3"),
+ RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo515, "vdd-l1-l4-l10"),
+ RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo, "vdd-l5-l16"),
+ RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo, "vdd-l6-l7"),
+ RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo, "vdd-l6-l7"),
+ RPMH_VREG("ldo8", LDO, 8, &pmic5_pldo, "vdd-l8-l9"),
+ RPMH_VREG("ldo9", LDO, 9, &pmic5_pldo, "vdd-l8-l9"),
+ RPMH_VREG("ldo10", LDO, 10, &pmic5_nldo515, "vdd-l1-l4-l10"),
+ RPMH_VREG("ldo11", LDO, 11, &pmic5_nldo515, "vdd-l11"),
+ RPMH_VREG("ldo12", LDO, 12, &pmic5_nldo515, "vdd-l12"),
+ RPMH_VREG("ldo13", LDO, 13, &pmic5_pldo, "vdd-l2-l13-l14"),
+ RPMH_VREG("ldo14", LDO, 14, &pmic5_pldo, "vdd-l2-l13-l14"),
+ RPMH_VREG("ldo15", LDO, 15, &pmic5_nldo515, "vdd-l15"),
+ RPMH_VREG("ldo16", LDO, 16, &pmic5_pldo, "vdd-l5-l16"),
+ RPMH_VREG("ldo17", LDO, 17, &pmic5_pldo, "vdd-l17"),
+ RPMH_VREG("bob1", BOB, 1, &pmic5_bob, "vdd-bob1"),
+ RPMH_VREG("bob2", BOB, 2, &pmic5_bob, "vdd-bob2"),
{}
};
static const struct rpmh_vreg_init_data pm8550vs_vreg_data[] = {
- RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps525, "vdd-s1"),
- RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps525, "vdd-s2"),
- RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps525, "vdd-s3"),
- RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps525, "vdd-s4"),
- RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps525, "vdd-s5"),
- RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps525, "vdd-s6"),
- RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-l1"),
- RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo515, "vdd-l2"),
- RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l3"),
+ RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps525, "vdd-s1"),
+ RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps525, "vdd-s2"),
+ RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps525, "vdd-s3"),
+ RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps525, "vdd-s4"),
+ RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps525, "vdd-s5"),
+ RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps525, "vdd-s6"),
+ RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo515, "vdd-l1"),
+ RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo515, "vdd-l2"),
+ RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo515, "vdd-l3"),
{}
};
static const struct rpmh_vreg_init_data pm8550ve_vreg_data[] = {
- RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps525, "vdd-s1"),
- RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps525, "vdd-s2"),
- RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps525, "vdd-s3"),
- RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps525, "vdd-s4"),
- RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps525, "vdd-s5"),
- RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps525, "vdd-s6"),
- RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps525, "vdd-s7"),
- RPMH_VREG("smps8", "smp%s8", &pmic5_ftsmps525, "vdd-s8"),
- RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-l1"),
- RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo515, "vdd-l2"),
- RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l3"),
+ RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps525, "vdd-s1"),
+ RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps525, "vdd-s2"),
+ RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps525, "vdd-s3"),
+ RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps525, "vdd-s4"),
+ RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps525, "vdd-s5"),
+ RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps525, "vdd-s6"),
+ RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps525, "vdd-s7"),
+ RPMH_VREG("smps8", SMPS, 8, &pmic5_ftsmps525, "vdd-s8"),
+ RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo515, "vdd-l1"),
+ RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo515, "vdd-l2"),
+ RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo515, "vdd-l3"),
{}
};
static const struct rpmh_vreg_init_data pmc8380_vreg_data[] = {
- RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps525, "vdd-s1"),
- RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps525, "vdd-s2"),
- RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps525, "vdd-s3"),
- RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps525, "vdd-s4"),
- RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps525, "vdd-s5"),
- RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps525, "vdd-s6"),
- RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps525, "vdd-s7"),
- RPMH_VREG("smps8", "smp%s8", &pmic5_ftsmps525, "vdd-s8"),
- RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-l1"),
- RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo515, "vdd-l2"),
- RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l3"),
+ RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps525, "vdd-s1"),
+ RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps525, "vdd-s2"),
+ RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps525, "vdd-s3"),
+ RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps525, "vdd-s4"),
+ RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps525, "vdd-s5"),
+ RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps525, "vdd-s6"),
+ RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps525, "vdd-s7"),
+ RPMH_VREG("smps8", SMPS, 8, &pmic5_ftsmps525, "vdd-s8"),
+ RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo515, "vdd-l1"),
+ RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo515, "vdd-l2"),
+ RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo515, "vdd-l3"),
{}
};
static const struct rpmh_vreg_init_data pm8009_vreg_data[] = {
- RPMH_VREG("smps1", "smp%s1", &pmic5_hfsmps510, "vdd-s1"),
- RPMH_VREG("smps2", "smp%s2", &pmic5_hfsmps515, "vdd-s2"),
- RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo, "vdd-l1"),
- RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo, "vdd-l2"),
- RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l3"),
- RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo, "vdd-l4"),
- RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo, "vdd-l5-l6"),
- RPMH_VREG("ldo6", "ldo%s6", &pmic5_pldo, "vdd-l5-l6"),
- RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo_lv, "vdd-l7"),
+ RPMH_VREG("smps1", SMPS, 1, &pmic5_hfsmps510, "vdd-s1"),
+ RPMH_VREG("smps2", SMPS, 2, &pmic5_hfsmps515, "vdd-s2"),
+ RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1"),
+ RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo, "vdd-l2"),
+ RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3"),
+ RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo, "vdd-l4"),
+ RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo, "vdd-l5-l6"),
+ RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo, "vdd-l5-l6"),
+ RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo_lv, "vdd-l7"),
{}
};
static const struct rpmh_vreg_init_data pm8009_1_vreg_data[] = {
- RPMH_VREG("smps1", "smp%s1", &pmic5_hfsmps510, "vdd-s1"),
- RPMH_VREG("smps2", "smp%s2", &pmic5_hfsmps515_1, "vdd-s2"),
- RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo, "vdd-l1"),
- RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo, "vdd-l2"),
- RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l3"),
- RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo, "vdd-l4"),
- RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo, "vdd-l5-l6"),
- RPMH_VREG("ldo6", "ldo%s6", &pmic5_pldo, "vdd-l5-l6"),
- RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo_lv, "vdd-l7"),
+ RPMH_VREG("smps1", SMPS, 1, &pmic5_hfsmps510, "vdd-s1"),
+ RPMH_VREG("smps2", SMPS, 2, &pmic5_hfsmps515_1, "vdd-s2"),
+ RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1"),
+ RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo, "vdd-l2"),
+ RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3"),
+ RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo, "vdd-l4"),
+ RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo, "vdd-l5-l6"),
+ RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo, "vdd-l5-l6"),
+ RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo_lv, "vdd-l7"),
{}
};
static const struct rpmh_vreg_init_data pm8010_vreg_data[] = {
- RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo502, "vdd-l1-l2"),
- RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo502, "vdd-l1-l2"),
- RPMH_VREG("ldo3", "ldo%s3", &pmic5_pldo502ln, "vdd-l3-l4"),
- RPMH_VREG("ldo4", "ldo%s4", &pmic5_pldo502ln, "vdd-l3-l4"),
- RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo502, "vdd-l5"),
- RPMH_VREG("ldo6", "ldo%s6", &pmic5_pldo502ln, "vdd-l6"),
- RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo502, "vdd-l7"),
+ RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo502, "vdd-l1-l2"),
+ RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo502, "vdd-l1-l2"),
+ RPMH_VREG("ldo3", LDO, 3, &pmic5_pldo502ln, "vdd-l3-l4"),
+ RPMH_VREG("ldo4", LDO, 4, &pmic5_pldo502ln, "vdd-l3-l4"),
+ RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo502, "vdd-l5"),
+ RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo502ln, "vdd-l6"),
+ RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo502, "vdd-l7"),
};
static const struct rpmh_vreg_init_data pm6150_vreg_data[] = {
- RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps510, "vdd-s1"),
- RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps510, "vdd-s2"),
- RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps510, "vdd-s3"),
- RPMH_VREG("smps4", "smp%s4", &pmic5_hfsmps510, "vdd-s4"),
- RPMH_VREG("smps5", "smp%s5", &pmic5_hfsmps510, "vdd-s5"),
- RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo, "vdd-l1"),
- RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo, "vdd-l2-l3"),
- RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l2-l3"),
- RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo, "vdd-l4-l7-l8"),
- RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo, "vdd-l5-l16-l17-l18-l19"),
- RPMH_VREG("ldo6", "ldo%s6", &pmic5_nldo, "vdd-l6"),
- RPMH_VREG("ldo7", "ldo%s7", &pmic5_nldo, "vdd-l4-l7-l8"),
- RPMH_VREG("ldo8", "ldo%s8", &pmic5_nldo, "vdd-l4-l7-l8"),
- RPMH_VREG("ldo9", "ldo%s9", &pmic5_nldo, "vdd-l9"),
- RPMH_VREG("ldo10", "ldo%s10", &pmic5_pldo_lv, "vdd-l10-l14-l15"),
- RPMH_VREG("ldo11", "ldo%s11", &pmic5_pldo_lv, "vdd-l11-l12-l13"),
- RPMH_VREG("ldo12", "ldo%s12", &pmic5_pldo_lv, "vdd-l11-l12-l13"),
- RPMH_VREG("ldo13", "ldo%s13", &pmic5_pldo_lv, "vdd-l11-l12-l13"),
- RPMH_VREG("ldo14", "ldo%s14", &pmic5_pldo_lv, "vdd-l10-l14-l15"),
- RPMH_VREG("ldo15", "ldo%s15", &pmic5_pldo_lv, "vdd-l10-l14-l15"),
- RPMH_VREG("ldo16", "ldo%s16", &pmic5_pldo, "vdd-l5-l16-l17-l18-l19"),
- RPMH_VREG("ldo17", "ldo%s17", &pmic5_pldo, "vdd-l5-l16-l17-l18-l19"),
- RPMH_VREG("ldo18", "ldo%s18", &pmic5_pldo, "vdd-l5-l16-l17-l18-l19"),
- RPMH_VREG("ldo19", "ldo%s19", &pmic5_pldo, "vdd-l5-l16-l17-l18-l19"),
+ RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps510, "vdd-s1"),
+ RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps510, "vdd-s2"),
+ RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps510, "vdd-s3"),
+ RPMH_VREG("smps4", SMPS, 4, &pmic5_hfsmps510, "vdd-s4"),
+ RPMH_VREG("smps5", SMPS, 5, &pmic5_hfsmps510, "vdd-s5"),
+ RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1"),
+ RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo, "vdd-l2-l3"),
+ RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l2-l3"),
+ RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo, "vdd-l4-l7-l8"),
+ RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo, "vdd-l5-l16-l17-l18-l19"),
+ RPMH_VREG("ldo6", LDO, 6, &pmic5_nldo, "vdd-l6"),
+ RPMH_VREG("ldo7", LDO, 7, &pmic5_nldo, "vdd-l4-l7-l8"),
+ RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo, "vdd-l4-l7-l8"),
+ RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo, "vdd-l9"),
+ RPMH_VREG("ldo10", LDO, 10, &pmic5_pldo_lv, "vdd-l10-l14-l15"),
+ RPMH_VREG("ldo11", LDO, 11, &pmic5_pldo_lv, "vdd-l11-l12-l13"),
+ RPMH_VREG("ldo12", LDO, 12, &pmic5_pldo_lv, "vdd-l11-l12-l13"),
+ RPMH_VREG("ldo13", LDO, 13, &pmic5_pldo_lv, "vdd-l11-l12-l13"),
+ RPMH_VREG("ldo14", LDO, 14, &pmic5_pldo_lv, "vdd-l10-l14-l15"),
+ RPMH_VREG("ldo15", LDO, 15, &pmic5_pldo_lv, "vdd-l10-l14-l15"),
+ RPMH_VREG("ldo16", LDO, 16, &pmic5_pldo, "vdd-l5-l16-l17-l18-l19"),
+ RPMH_VREG("ldo17", LDO, 17, &pmic5_pldo, "vdd-l5-l16-l17-l18-l19"),
+ RPMH_VREG("ldo18", LDO, 18, &pmic5_pldo, "vdd-l5-l16-l17-l18-l19"),
+ RPMH_VREG("ldo19", LDO, 19, &pmic5_pldo, "vdd-l5-l16-l17-l18-l19"),
{}
};
static const struct rpmh_vreg_init_data pm6150l_vreg_data[] = {
- RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps510, "vdd-s1"),
- RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps510, "vdd-s2"),
- RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps510, "vdd-s3"),
- RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps510, "vdd-s4"),
- RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps510, "vdd-s5"),
- RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps510, "vdd-s6"),
- RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps510, "vdd-s7"),
- RPMH_VREG("smps8", "smp%s8", &pmic5_hfsmps510, "vdd-s8"),
- RPMH_VREG("ldo1", "ldo%s1", &pmic5_pldo_lv, "vdd-l1-l8"),
- RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo, "vdd-l2-l3"),
- RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l2-l3"),
- RPMH_VREG("ldo4", "ldo%s4", &pmic5_pldo, "vdd-l4-l5-l6"),
- RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo, "vdd-l4-l5-l6"),
- RPMH_VREG("ldo6", "ldo%s6", &pmic5_pldo, "vdd-l4-l5-l6"),
- RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo, "vdd-l7-l11"),
- RPMH_VREG("ldo8", "ldo%s8", &pmic5_pldo, "vdd-l1-l8"),
- RPMH_VREG("ldo9", "ldo%s9", &pmic5_pldo, "vdd-l9-l10"),
- RPMH_VREG("ldo10", "ldo%s10", &pmic5_pldo, "vdd-l9-l10"),
- RPMH_VREG("ldo11", "ldo%s11", &pmic5_pldo, "vdd-l7-l11"),
- RPMH_VREG("bob", "bob%s1", &pmic5_bob, "vdd-bob"),
+ RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps510, "vdd-s1"),
+ RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps510, "vdd-s2"),
+ RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps510, "vdd-s3"),
+ RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps510, "vdd-s4"),
+ RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps510, "vdd-s5"),
+ RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps510, "vdd-s6"),
+ RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps510, "vdd-s7"),
+ RPMH_VREG("smps8", SMPS, 8, &pmic5_hfsmps510, "vdd-s8"),
+ RPMH_VREG("ldo1", LDO, 1, &pmic5_pldo_lv, "vdd-l1-l8"),
+ RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo, "vdd-l2-l3"),
+ RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l2-l3"),
+ RPMH_VREG("ldo4", LDO, 4, &pmic5_pldo, "vdd-l4-l5-l6"),
+ RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo, "vdd-l4-l5-l6"),
+ RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo, "vdd-l4-l5-l6"),
+ RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo, "vdd-l7-l11"),
+ RPMH_VREG("ldo8", LDO, 8, &pmic5_pldo, "vdd-l1-l8"),
+ RPMH_VREG("ldo9", LDO, 9, &pmic5_pldo, "vdd-l9-l10"),
+ RPMH_VREG("ldo10", LDO, 10, &pmic5_pldo, "vdd-l9-l10"),
+ RPMH_VREG("ldo11", LDO, 11, &pmic5_pldo, "vdd-l7-l11"),
+ RPMH_VREG("bob", BOB, 1, &pmic5_bob, "vdd-bob"),
{}
};
static const struct rpmh_vreg_init_data pm6350_vreg_data[] = {
- RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps510, NULL),
- RPMH_VREG("smps2", "smp%s2", &pmic5_hfsmps510, NULL),
+ RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps510, NULL),
+ RPMH_VREG("smps2", SMPS, 2, &pmic5_hfsmps510, NULL),
/* smps3 - smps5 not configured */
- RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo, NULL),
- RPMH_VREG("ldo2", "ldo%s2", &pmic5_pldo, NULL),
- RPMH_VREG("ldo3", "ldo%s3", &pmic5_pldo, NULL),
- RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo, NULL),
- RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo, NULL),
- RPMH_VREG("ldo6", "ldo%s6", &pmic5_pldo, NULL),
- RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo, NULL),
- RPMH_VREG("ldo8", "ldo%s8", &pmic5_pldo, NULL),
- RPMH_VREG("ldo9", "ldo%s9", &pmic5_pldo, NULL),
- RPMH_VREG("ldo10", "ldo%s10", &pmic5_pldo, NULL),
- RPMH_VREG("ldo11", "ldo%s11", &pmic5_pldo, NULL),
- RPMH_VREG("ldo12", "ldo%s12", &pmic5_pldo, NULL),
- RPMH_VREG("ldo13", "ldo%s13", &pmic5_nldo, NULL),
- RPMH_VREG("ldo14", "ldo%s14", &pmic5_pldo, NULL),
- RPMH_VREG("ldo15", "ldo%s15", &pmic5_nldo, NULL),
- RPMH_VREG("ldo16", "ldo%s16", &pmic5_nldo, NULL),
+ RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, NULL),
+ RPMH_VREG("ldo2", LDO, 2, &pmic5_pldo, NULL),
+ RPMH_VREG("ldo3", LDO, 3, &pmic5_pldo, NULL),
+ RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo, NULL),
+ RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo, NULL),
+ RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo, NULL),
+ RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo, NULL),
+ RPMH_VREG("ldo8", LDO, 8, &pmic5_pldo, NULL),
+ RPMH_VREG("ldo9", LDO, 9, &pmic5_pldo, NULL),
+ RPMH_VREG("ldo10", LDO, 10, &pmic5_pldo, NULL),
+ RPMH_VREG("ldo11", LDO, 11, &pmic5_pldo, NULL),
+ RPMH_VREG("ldo12", LDO, 12, &pmic5_pldo, NULL),
+ RPMH_VREG("ldo13", LDO, 13, &pmic5_nldo, NULL),
+ RPMH_VREG("ldo14", LDO, 14, &pmic5_pldo, NULL),
+ RPMH_VREG("ldo15", LDO, 15, &pmic5_nldo, NULL),
+ RPMH_VREG("ldo16", LDO, 16, &pmic5_nldo, NULL),
/* ldo17 not configured */
- RPMH_VREG("ldo18", "ldo%s18", &pmic5_nldo, NULL),
- RPMH_VREG("ldo19", "ldo%s19", &pmic5_nldo, NULL),
- RPMH_VREG("ldo20", "ldo%s20", &pmic5_nldo, NULL),
- RPMH_VREG("ldo21", "ldo%s21", &pmic5_nldo, NULL),
- RPMH_VREG("ldo22", "ldo%s22", &pmic5_nldo, NULL),
+ RPMH_VREG("ldo18", LDO, 18, &pmic5_nldo, NULL),
+ RPMH_VREG("ldo19", LDO, 19, &pmic5_nldo, NULL),
+ RPMH_VREG("ldo20", LDO, 20, &pmic5_nldo, NULL),
+ RPMH_VREG("ldo21", LDO, 21, &pmic5_nldo, NULL),
+ RPMH_VREG("ldo22", LDO, 22, &pmic5_nldo, NULL),
};
static const struct rpmh_vreg_init_data pmx55_vreg_data[] = {
- RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps510, "vdd-s1"),
- RPMH_VREG("smps2", "smp%s2", &pmic5_hfsmps510, "vdd-s2"),
- RPMH_VREG("smps3", "smp%s3", &pmic5_hfsmps510, "vdd-s3"),
- RPMH_VREG("smps4", "smp%s4", &pmic5_hfsmps510, "vdd-s4"),
- RPMH_VREG("smps5", "smp%s5", &pmic5_hfsmps510, "vdd-s5"),
- RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps510, "vdd-s6"),
- RPMH_VREG("smps7", "smp%s7", &pmic5_hfsmps510, "vdd-s7"),
- RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo, "vdd-l1-l2"),
- RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo, "vdd-l1-l2"),
- RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l3-l9"),
- RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo, "vdd-l4-l12"),
- RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo, "vdd-l5-l6"),
- RPMH_VREG("ldo6", "ldo%s6", &pmic5_pldo, "vdd-l5-l6"),
- RPMH_VREG("ldo7", "ldo%s7", &pmic5_nldo, "vdd-l7-l8"),
- RPMH_VREG("ldo8", "ldo%s8", &pmic5_nldo, "vdd-l7-l8"),
- RPMH_VREG("ldo9", "ldo%s9", &pmic5_nldo, "vdd-l3-l9"),
- RPMH_VREG("ldo10", "ldo%s10", &pmic5_pldo, "vdd-l10-l11-l13"),
- RPMH_VREG("ldo11", "ldo%s11", &pmic5_pldo, "vdd-l10-l11-l13"),
- RPMH_VREG("ldo12", "ldo%s12", &pmic5_nldo, "vdd-l4-l12"),
- RPMH_VREG("ldo13", "ldo%s13", &pmic5_pldo, "vdd-l10-l11-l13"),
- RPMH_VREG("ldo14", "ldo%s14", &pmic5_nldo, "vdd-l14"),
- RPMH_VREG("ldo15", "ldo%s15", &pmic5_nldo, "vdd-l15"),
- RPMH_VREG("ldo16", "ldo%s16", &pmic5_pldo, "vdd-l16"),
+ RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps510, "vdd-s1"),
+ RPMH_VREG("smps2", SMPS, 2, &pmic5_hfsmps510, "vdd-s2"),
+ RPMH_VREG("smps3", SMPS, 3, &pmic5_hfsmps510, "vdd-s3"),
+ RPMH_VREG("smps4", SMPS, 4, &pmic5_hfsmps510, "vdd-s4"),
+ RPMH_VREG("smps5", SMPS, 5, &pmic5_hfsmps510, "vdd-s5"),
+ RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps510, "vdd-s6"),
+ RPMH_VREG("smps7", SMPS, 7, &pmic5_hfsmps510, "vdd-s7"),
+ RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1-l2"),
+ RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo, "vdd-l1-l2"),
+ RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3-l9"),
+ RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo, "vdd-l4-l12"),
+ RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo, "vdd-l5-l6"),
+ RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo, "vdd-l5-l6"),
+ RPMH_VREG("ldo7", LDO, 7, &pmic5_nldo, "vdd-l7-l8"),
+ RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo, "vdd-l7-l8"),
+ RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo, "vdd-l3-l9"),
+ RPMH_VREG("ldo10", LDO, 10, &pmic5_pldo, "vdd-l10-l11-l13"),
+ RPMH_VREG("ldo11", LDO, 11, &pmic5_pldo, "vdd-l10-l11-l13"),
+ RPMH_VREG("ldo12", LDO, 12, &pmic5_nldo, "vdd-l4-l12"),
+ RPMH_VREG("ldo13", LDO, 13, &pmic5_pldo, "vdd-l10-l11-l13"),
+ RPMH_VREG("ldo14", LDO, 14, &pmic5_nldo, "vdd-l14"),
+ RPMH_VREG("ldo15", LDO, 15, &pmic5_nldo, "vdd-l15"),
+ RPMH_VREG("ldo16", LDO, 16, &pmic5_pldo, "vdd-l16"),
{}
};
static const struct rpmh_vreg_init_data pmx65_vreg_data[] = {
- RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps510, "vdd-s1"),
- RPMH_VREG("smps2", "smp%s2", &pmic5_hfsmps510, "vdd-s2"),
- RPMH_VREG("smps3", "smp%s3", &pmic5_hfsmps510, "vdd-s3"),
- RPMH_VREG("smps4", "smp%s4", &pmic5_hfsmps510, "vdd-s4"),
- RPMH_VREG("smps5", "smp%s5", &pmic5_hfsmps510, "vdd-s5"),
- RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps510, "vdd-s6"),
- RPMH_VREG("smps7", "smp%s7", &pmic5_hfsmps510, "vdd-s7"),
- RPMH_VREG("smps8", "smp%s8", &pmic5_hfsmps510, "vdd-s8"),
- RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo, "vdd-l1"),
- RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo, "vdd-l2-l18"),
- RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l3"),
- RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo, "vdd-l4"),
- RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo, "vdd-l5-l6-l16"),
- RPMH_VREG("ldo6", "ldo%s6", &pmic5_pldo, "vdd-l5-l6-l16"),
- RPMH_VREG("ldo7", "ldo%s7", &pmic5_nldo, "vdd-l7"),
- RPMH_VREG("ldo8", "ldo%s8", &pmic5_nldo, "vdd-l8-l9"),
- RPMH_VREG("ldo9", "ldo%s9", &pmic5_nldo, "vdd-l8-l9"),
- RPMH_VREG("ldo10", "ldo%s10", &pmic5_pldo, "vdd-l10"),
- RPMH_VREG("ldo11", "ldo%s11", &pmic5_pldo, "vdd-l11-l13"),
- RPMH_VREG("ldo12", "ldo%s12", &pmic5_nldo, "vdd-l12"),
- RPMH_VREG("ldo13", "ldo%s13", &pmic5_pldo, "vdd-l11-l13"),
- RPMH_VREG("ldo14", "ldo%s14", &pmic5_nldo, "vdd-l14"),
- RPMH_VREG("ldo15", "ldo%s15", &pmic5_nldo, "vdd-l15"),
- RPMH_VREG("ldo16", "ldo%s16", &pmic5_pldo, "vdd-l5-l6-l16"),
- RPMH_VREG("ldo17", "ldo%s17", &pmic5_nldo, "vdd-l17"),
+ RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps510, "vdd-s1"),
+ RPMH_VREG("smps2", SMPS, 2, &pmic5_hfsmps510, "vdd-s2"),
+ RPMH_VREG("smps3", SMPS, 3, &pmic5_hfsmps510, "vdd-s3"),
+ RPMH_VREG("smps4", SMPS, 4, &pmic5_hfsmps510, "vdd-s4"),
+ RPMH_VREG("smps5", SMPS, 5, &pmic5_hfsmps510, "vdd-s5"),
+ RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps510, "vdd-s6"),
+ RPMH_VREG("smps7", SMPS, 7, &pmic5_hfsmps510, "vdd-s7"),
+ RPMH_VREG("smps8", SMPS, 8, &pmic5_hfsmps510, "vdd-s8"),
+ RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1"),
+ RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo, "vdd-l2-l18"),
+ RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3"),
+ RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo, "vdd-l4"),
+ RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo, "vdd-l5-l6-l16"),
+ RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo, "vdd-l5-l6-l16"),
+ RPMH_VREG("ldo7", LDO, 7, &pmic5_nldo, "vdd-l7"),
+ RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo, "vdd-l8-l9"),
+ RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo, "vdd-l8-l9"),
+ RPMH_VREG("ldo10", LDO, 10, &pmic5_pldo, "vdd-l10"),
+ RPMH_VREG("ldo11", LDO, 11, &pmic5_pldo, "vdd-l11-l13"),
+ RPMH_VREG("ldo12", LDO, 12, &pmic5_nldo, "vdd-l12"),
+ RPMH_VREG("ldo13", LDO, 13, &pmic5_pldo, "vdd-l11-l13"),
+ RPMH_VREG("ldo14", LDO, 14, &pmic5_nldo, "vdd-l14"),
+ RPMH_VREG("ldo15", LDO, 15, &pmic5_nldo, "vdd-l15"),
+ RPMH_VREG("ldo16", LDO, 16, &pmic5_pldo, "vdd-l5-l6-l16"),
+ RPMH_VREG("ldo17", LDO, 17, &pmic5_nldo, "vdd-l17"),
/* ldo18 not configured */
- RPMH_VREG("ldo19", "ldo%s19", &pmic5_nldo, "vdd-l19"),
- RPMH_VREG("ldo20", "ldo%s20", &pmic5_nldo, "vdd-l20"),
- RPMH_VREG("ldo21", "ldo%s21", &pmic5_nldo, "vdd-l21"),
+ RPMH_VREG("ldo19", LDO, 19, &pmic5_nldo, "vdd-l19"),
+ RPMH_VREG("ldo20", LDO, 20, &pmic5_nldo, "vdd-l20"),
+ RPMH_VREG("ldo21", LDO, 21, &pmic5_nldo, "vdd-l21"),
{}
};
static const struct rpmh_vreg_init_data pmx75_vreg_data[] = {
- RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps525, "vdd-s1"),
- RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps525, "vdd-s2"),
- RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps525, "vdd-s3"),
- RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps525, "vdd-s4"),
- RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps525, "vdd-s5"),
- RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps525, "vdd-s6"),
- RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps525, "vdd-s7"),
- RPMH_VREG("smps8", "smp%s8", &pmic5_ftsmps525, "vdd-s8"),
- RPMH_VREG("smps9", "smp%s9", &pmic5_ftsmps525, "vdd-s9"),
- RPMH_VREG("smps10", "smp%s10", &pmic5_ftsmps525, "vdd-s10"),
- RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-l1"),
- RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo515, "vdd-l2-18"),
- RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l3"),
- RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo515, "vdd-l4-l16"),
- RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo_lv, "vdd-l5-l6"),
- RPMH_VREG("ldo6", "ldo%s6", &pmic5_pldo_lv, "vdd-l5-l6"),
- RPMH_VREG("ldo7", "ldo%s7", &pmic5_nldo515, "vdd-l7"),
- RPMH_VREG("ldo8", "ldo%s8", &pmic5_nldo515, "vdd-l8-l9"),
- RPMH_VREG("ldo9", "ldo%s9", &pmic5_nldo515, "vdd-l8-l9"),
- RPMH_VREG("ldo10", "ldo%s10", &pmic5_pldo, "vdd-l10"),
- RPMH_VREG("ldo11", "ldo%s11", &pmic5_pldo, "vdd-l11-l13"),
- RPMH_VREG("ldo12", "ldo%s12", &pmic5_nldo515, "vdd-l12"),
- RPMH_VREG("ldo13", "ldo%s13", &pmic5_pldo, "vdd-l11-l13"),
- RPMH_VREG("ldo14", "ldo%s14", &pmic5_nldo515, "vdd-l14"),
- RPMH_VREG("ldo15", "ldo%s15", &pmic5_nldo515, "vdd-l15"),
- RPMH_VREG("ldo16", "ldo%s16", &pmic5_nldo515, "vdd-l4-l16"),
- RPMH_VREG("ldo17", "ldo%s17", &pmic5_nldo515, "vdd-l17"),
+ RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps525, "vdd-s1"),
+ RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps525, "vdd-s2"),
+ RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps525, "vdd-s3"),
+ RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps525, "vdd-s4"),
+ RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps525, "vdd-s5"),
+ RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps525, "vdd-s6"),
+ RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps525, "vdd-s7"),
+ RPMH_VREG("smps8", SMPS, 8, &pmic5_ftsmps525, "vdd-s8"),
+ RPMH_VREG("smps9", SMPS, 9, &pmic5_ftsmps525, "vdd-s9"),
+ RPMH_VREG("smps10", SMPS, 10, &pmic5_ftsmps525, "vdd-s10"),
+ RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo515, "vdd-l1"),
+ RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo515, "vdd-l2-18"),
+ RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo515, "vdd-l3"),
+ RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo515, "vdd-l4-l16"),
+ RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo_lv, "vdd-l5-l6"),
+ RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo_lv, "vdd-l5-l6"),
+ RPMH_VREG("ldo7", LDO, 7, &pmic5_nldo515, "vdd-l7"),
+ RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo515, "vdd-l8-l9"),
+ RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo515, "vdd-l8-l9"),
+ RPMH_VREG("ldo10", LDO, 10, &pmic5_pldo, "vdd-l10"),
+ RPMH_VREG("ldo11", LDO, 11, &pmic5_pldo, "vdd-l11-l13"),
+ RPMH_VREG("ldo12", LDO, 12, &pmic5_nldo515, "vdd-l12"),
+ RPMH_VREG("ldo13", LDO, 13, &pmic5_pldo, "vdd-l11-l13"),
+ RPMH_VREG("ldo14", LDO, 14, &pmic5_nldo515, "vdd-l14"),
+ RPMH_VREG("ldo15", LDO, 15, &pmic5_nldo515, "vdd-l15"),
+ RPMH_VREG("ldo16", LDO, 16, &pmic5_nldo515, "vdd-l4-l16"),
+ RPMH_VREG("ldo17", LDO, 17, &pmic5_nldo515, "vdd-l17"),
/* ldo18 not configured */
- RPMH_VREG("ldo19", "ldo%s19", &pmic5_nldo515, "vdd-l19"),
- RPMH_VREG("ldo20", "ldo%s20", &pmic5_nldo515, "vdd-l20-l21"),
- RPMH_VREG("ldo21", "ldo%s21", &pmic5_nldo515, "vdd-l20-l21"),
+ RPMH_VREG("ldo19", LDO, 19, &pmic5_nldo515, "vdd-l19"),
+ RPMH_VREG("ldo20", LDO, 20, &pmic5_nldo515, "vdd-l20-l21"),
+ RPMH_VREG("ldo21", LDO, 21, &pmic5_nldo515, "vdd-l20-l21"),
};
static const struct rpmh_vreg_init_data pm7325_vreg_data[] = {
- RPMH_VREG("smps1", "smp%s1", &pmic5_hfsmps510, "vdd-s1"),
- RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps520, "vdd-s2"),
- RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps520, "vdd-s3"),
- RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps520, "vdd-s4"),
- RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps520, "vdd-s5"),
- RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps520, "vdd-s6"),
- RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps520, "vdd-s7"),
- RPMH_VREG("smps8", "smp%s8", &pmic5_hfsmps510, "vdd-s8"),
- RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo, "vdd-l1-l4-l12-l15"),
- RPMH_VREG("ldo2", "ldo%s2", &pmic5_pldo, "vdd-l2-l7"),
- RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l3"),
- RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo, "vdd-l1-l4-l12-l15"),
- RPMH_VREG("ldo5", "ldo%s5", &pmic5_nldo, "vdd-l5"),
- RPMH_VREG("ldo6", "ldo%s6", &pmic5_nldo, "vdd-l6-l9-l10"),
- RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo, "vdd-l2-l7"),
- RPMH_VREG("ldo8", "ldo%s8", &pmic5_nldo, "vdd-l8"),
- RPMH_VREG("ldo9", "ldo%s9", &pmic5_nldo, "vdd-l6-l9-l10"),
- RPMH_VREG("ldo10", "ldo%s10", &pmic5_nldo, "vdd-l6-l9-l10"),
- RPMH_VREG("ldo11", "ldo%s11", &pmic5_pldo_lv, "vdd-l11-l17-l18-l19"),
- RPMH_VREG("ldo12", "ldo%s12", &pmic5_nldo, "vdd-l1-l4-l12-l15"),
- RPMH_VREG("ldo13", "ldo%s13", &pmic5_nldo, "vdd-l13"),
- RPMH_VREG("ldo14", "ldo%s14", &pmic5_nldo, "vdd-l14-l16"),
- RPMH_VREG("ldo15", "ldo%s15", &pmic5_nldo, "vdd-l1-l4-l12-l15"),
- RPMH_VREG("ldo16", "ldo%s16", &pmic5_nldo, "vdd-l14-l16"),
- RPMH_VREG("ldo17", "ldo%s17", &pmic5_pldo_lv, "vdd-l11-l17-l18-l19"),
- RPMH_VREG("ldo18", "ldo%s18", &pmic5_pldo_lv, "vdd-l11-l17-l18-l19"),
- RPMH_VREG("ldo19", "ldo%s19", &pmic5_pldo_lv, "vdd-l11-l17-l18-l19"),
+ RPMH_VREG("smps1", SMPS, 1, &pmic5_hfsmps510, "vdd-s1"),
+ RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps520, "vdd-s2"),
+ RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps520, "vdd-s3"),
+ RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps520, "vdd-s4"),
+ RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps520, "vdd-s5"),
+ RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps520, "vdd-s6"),
+ RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps520, "vdd-s7"),
+ RPMH_VREG("smps8", SMPS, 8, &pmic5_hfsmps510, "vdd-s8"),
+ RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1-l4-l12-l15"),
+ RPMH_VREG("ldo2", LDO, 2, &pmic5_pldo, "vdd-l2-l7"),
+ RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3"),
+ RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo, "vdd-l1-l4-l12-l15"),
+ RPMH_VREG("ldo5", LDO, 5, &pmic5_nldo, "vdd-l5"),
+ RPMH_VREG("ldo6", LDO, 6, &pmic5_nldo, "vdd-l6-l9-l10"),
+ RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo, "vdd-l2-l7"),
+ RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo, "vdd-l8"),
+ RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo, "vdd-l6-l9-l10"),
+ RPMH_VREG("ldo10", LDO, 10, &pmic5_nldo, "vdd-l6-l9-l10"),
+ RPMH_VREG("ldo11", LDO, 11, &pmic5_pldo_lv, "vdd-l11-l17-l18-l19"),
+ RPMH_VREG("ldo12", LDO, 12, &pmic5_nldo, "vdd-l1-l4-l12-l15"),
+ RPMH_VREG("ldo13", LDO, 13, &pmic5_nldo, "vdd-l13"),
+ RPMH_VREG("ldo14", LDO, 14, &pmic5_nldo, "vdd-l14-l16"),
+ RPMH_VREG("ldo15", LDO, 15, &pmic5_nldo, "vdd-l1-l4-l12-l15"),
+ RPMH_VREG("ldo16", LDO, 16, &pmic5_nldo, "vdd-l14-l16"),
+ RPMH_VREG("ldo17", LDO, 17, &pmic5_pldo_lv, "vdd-l11-l17-l18-l19"),
+ RPMH_VREG("ldo18", LDO, 18, &pmic5_pldo_lv, "vdd-l11-l17-l18-l19"),
+ RPMH_VREG("ldo19", LDO, 19, &pmic5_pldo_lv, "vdd-l11-l17-l18-l19"),
{}
};
static const struct rpmh_vreg_init_data pm7550_vreg_data[] = {
- RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps525, "vdd-s1"),
- RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps525, "vdd-s2"),
- RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps525, "vdd-s3"),
- RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps525, "vdd-s4"),
- RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps525, "vdd-s5"),
- RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps525, "vdd-s6"),
- RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-l1"),
- RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo515, "vdd-l2-l3"),
- RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l2-l3"),
- RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo515, "vdd-l4-l5"),
- RPMH_VREG("ldo5", "ldo%s5", &pmic5_nldo515, "vdd-l4-l5"),
- RPMH_VREG("ldo6", "ldo%s6", &pmic5_nldo515, "vdd-l6"),
- RPMH_VREG("ldo7", "ldo%s7", &pmic5_nldo515, "vdd-l7"),
- RPMH_VREG("ldo8", "ldo%s8", &pmic5_nldo515, "vdd-l8"),
- RPMH_VREG("ldo9", "ldo%s9", &pmic5_nldo515, "vdd-l9-l10"),
- RPMH_VREG("ldo10", "ldo%s10", &pmic5_nldo515, "vdd-l9-l10"),
- RPMH_VREG("ldo11", "ldo%s11", &pmic5_nldo515, "vdd-l11"),
- RPMH_VREG("ldo12", "ldo%s12", &pmic5_pldo515_mv, "vdd-l12-l14"),
- RPMH_VREG("ldo13", "ldo%s13", &pmic5_pldo515_mv, "vdd-l13-l16"),
- RPMH_VREG("ldo14", "ldo%s14", &pmic5_pldo, "vdd-l12-l14"),
- RPMH_VREG("ldo15", "ldo%s15", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
- RPMH_VREG("ldo16", "ldo%s16", &pmic5_pldo, "vdd-l13-l16"),
- RPMH_VREG("ldo17", "ldo%s17", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
- RPMH_VREG("ldo18", "ldo%s18", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
- RPMH_VREG("ldo19", "ldo%s19", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
- RPMH_VREG("ldo20", "ldo%s20", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
- RPMH_VREG("ldo21", "ldo%s21", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
- RPMH_VREG("ldo22", "ldo%s22", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
- RPMH_VREG("ldo23", "ldo%s23", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
- RPMH_VREG("bob", "bob%s1", &pmic5_bob, "vdd-bob"),
+ RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps525, "vdd-s1"),
+ RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps525, "vdd-s2"),
+ RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps525, "vdd-s3"),
+ RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps525, "vdd-s4"),
+ RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps525, "vdd-s5"),
+ RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps525, "vdd-s6"),
+ RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo515, "vdd-l1"),
+ RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo515, "vdd-l2-l3"),
+ RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo515, "vdd-l2-l3"),
+ RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo515, "vdd-l4-l5"),
+ RPMH_VREG("ldo5", LDO, 5, &pmic5_nldo515, "vdd-l4-l5"),
+ RPMH_VREG("ldo6", LDO, 6, &pmic5_nldo515, "vdd-l6"),
+ RPMH_VREG("ldo7", LDO, 7, &pmic5_nldo515, "vdd-l7"),
+ RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo515, "vdd-l8"),
+ RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo515, "vdd-l9-l10"),
+ RPMH_VREG("ldo10", LDO, 10, &pmic5_nldo515, "vdd-l9-l10"),
+ RPMH_VREG("ldo11", LDO, 11, &pmic5_nldo515, "vdd-l11"),
+ RPMH_VREG("ldo12", LDO, 12, &pmic5_pldo515_mv, "vdd-l12-l14"),
+ RPMH_VREG("ldo13", LDO, 13, &pmic5_pldo515_mv, "vdd-l13-l16"),
+ RPMH_VREG("ldo14", LDO, 14, &pmic5_pldo, "vdd-l12-l14"),
+ RPMH_VREG("ldo15", LDO, 15, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
+ RPMH_VREG("ldo16", LDO, 16, &pmic5_pldo, "vdd-l13-l16"),
+ RPMH_VREG("ldo17", LDO, 17, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
+ RPMH_VREG("ldo18", LDO, 18, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
+ RPMH_VREG("ldo19", LDO, 19, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
+ RPMH_VREG("ldo20", LDO, 20, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
+ RPMH_VREG("ldo21", LDO, 21, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
+ RPMH_VREG("ldo22", LDO, 22, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
+ RPMH_VREG("ldo23", LDO, 23, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
+ RPMH_VREG("bob", BOB, 1, &pmic5_bob, "vdd-bob"),
{}
};
static const struct rpmh_vreg_init_data pmr735a_vreg_data[] = {
- RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps520, "vdd-s1"),
- RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps520, "vdd-s2"),
- RPMH_VREG("smps3", "smp%s3", &pmic5_hfsmps515, "vdd-s3"),
- RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo, "vdd-l1-l2"),
- RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo, "vdd-l1-l2"),
- RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l3"),
- RPMH_VREG("ldo4", "ldo%s4", &pmic5_pldo_lv, "vdd-l4"),
- RPMH_VREG("ldo5", "ldo%s5", &pmic5_nldo, "vdd-l5-l6"),
- RPMH_VREG("ldo6", "ldo%s6", &pmic5_nldo, "vdd-l5-l6"),
- RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo, "vdd-l7-bob"),
+ RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps520, "vdd-s1"),
+ RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps520, "vdd-s2"),
+ RPMH_VREG("smps3", SMPS, 3, &pmic5_hfsmps515, "vdd-s3"),
+ RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1-l2"),
+ RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo, "vdd-l1-l2"),
+ RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3"),
+ RPMH_VREG("ldo4", LDO, 4, &pmic5_pldo_lv, "vdd-l4"),
+ RPMH_VREG("ldo5", LDO, 5, &pmic5_nldo, "vdd-l5-l6"),
+ RPMH_VREG("ldo6", LDO, 6, &pmic5_nldo, "vdd-l5-l6"),
+ RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo, "vdd-l7-bob"),
{}
};
static const struct rpmh_vreg_init_data pmr735b_vreg_data[] = {
- RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo, "vdd-l1-l2"),
- RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo, "vdd-l1-l2"),
- RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l3"),
- RPMH_VREG("ldo4", "ldo%s4", &pmic5_pldo_lv, "vdd-l4"),
- RPMH_VREG("ldo5", "ldo%s5", &pmic5_nldo, "vdd-l5"),
- RPMH_VREG("ldo6", "ldo%s6", &pmic5_nldo, "vdd-l6"),
- RPMH_VREG("ldo7", "ldo%s7", &pmic5_nldo, "vdd-l7-l8"),
- RPMH_VREG("ldo8", "ldo%s8", &pmic5_nldo, "vdd-l7-l8"),
- RPMH_VREG("ldo9", "ldo%s9", &pmic5_nldo, "vdd-l9"),
- RPMH_VREG("ldo10", "ldo%s10", &pmic5_pldo_lv, "vdd-l10"),
- RPMH_VREG("ldo11", "ldo%s11", &pmic5_nldo, "vdd-l11"),
- RPMH_VREG("ldo12", "ldo%s12", &pmic5_nldo, "vdd-l12"),
+ RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1-l2"),
+ RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo, "vdd-l1-l2"),
+ RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3"),
+ RPMH_VREG("ldo4", LDO, 4, &pmic5_pldo_lv, "vdd-l4"),
+ RPMH_VREG("ldo5", LDO, 5, &pmic5_nldo, "vdd-l5"),
+ RPMH_VREG("ldo6", LDO, 6, &pmic5_nldo, "vdd-l6"),
+ RPMH_VREG("ldo7", LDO, 7, &pmic5_nldo, "vdd-l7-l8"),
+ RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo, "vdd-l7-l8"),
+ RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo, "vdd-l9"),
+ RPMH_VREG("ldo10", LDO, 10, &pmic5_pldo_lv, "vdd-l10"),
+ RPMH_VREG("ldo11", LDO, 11, &pmic5_nldo, "vdd-l11"),
+ RPMH_VREG("ldo12", LDO, 12, &pmic5_nldo, "vdd-l12"),
{}
};
static const struct rpmh_vreg_init_data pm660_vreg_data[] = {
- RPMH_VREG("smps1", "smp%s1", &pmic4_ftsmps426, "vdd-s1"),
- RPMH_VREG("smps2", "smp%s2", &pmic4_ftsmps426, "vdd-s2"),
- RPMH_VREG("smps3", "smp%s3", &pmic4_ftsmps426, "vdd-s3"),
- RPMH_VREG("smps4", "smp%s4", &pmic4_hfsmps3, "vdd-s4"),
- RPMH_VREG("smps5", "smp%s5", &pmic4_hfsmps3, "vdd-s5"),
- RPMH_VREG("smps6", "smp%s6", &pmic4_hfsmps3, "vdd-s6"),
- RPMH_VREG("ldo1", "ldo%s1", &pmic4_nldo, "vdd-l1-l6-l7"),
- RPMH_VREG("ldo2", "ldo%s2", &pmic4_nldo, "vdd-l2-l3"),
- RPMH_VREG("ldo3", "ldo%s3", &pmic4_nldo, "vdd-l2-l3"),
+ RPMH_VREG("smps1", SMPS, 1, &pmic4_ftsmps426, "vdd-s1"),
+ RPMH_VREG("smps2", SMPS, 2, &pmic4_ftsmps426, "vdd-s2"),
+ RPMH_VREG("smps3", SMPS, 3, &pmic4_ftsmps426, "vdd-s3"),
+ RPMH_VREG("smps4", SMPS, 4, &pmic4_hfsmps3, "vdd-s4"),
+ RPMH_VREG("smps5", SMPS, 5, &pmic4_hfsmps3, "vdd-s5"),
+ RPMH_VREG("smps6", SMPS, 6, &pmic4_hfsmps3, "vdd-s6"),
+ RPMH_VREG("ldo1", LDO, 1, &pmic4_nldo, "vdd-l1-l6-l7"),
+ RPMH_VREG("ldo2", LDO, 2, &pmic4_nldo, "vdd-l2-l3"),
+ RPMH_VREG("ldo3", LDO, 3, &pmic4_nldo, "vdd-l2-l3"),
/* ldo4 is inaccessible on PM660 */
- RPMH_VREG("ldo5", "ldo%s5", &pmic4_nldo, "vdd-l5"),
- RPMH_VREG("ldo6", "ldo%s6", &pmic4_nldo, "vdd-l1-l6-l7"),
- RPMH_VREG("ldo7", "ldo%s7", &pmic4_nldo, "vdd-l1-l6-l7"),
- RPMH_VREG("ldo8", "ldo%s8", &pmic4_pldo_lv, "vdd-l8-l9-l10-l11-l12-l13-l14"),
- RPMH_VREG("ldo9", "ldo%s9", &pmic4_pldo_lv, "vdd-l8-l9-l10-l11-l12-l13-l14"),
- RPMH_VREG("ldo10", "ldo%s10", &pmic4_pldo_lv, "vdd-l8-l9-l10-l11-l12-l13-l14"),
- RPMH_VREG("ldo11", "ldo%s11", &pmic4_pldo_lv, "vdd-l8-l9-l10-l11-l12-l13-l14"),
- RPMH_VREG("ldo12", "ldo%s12", &pmic4_pldo_lv, "vdd-l8-l9-l10-l11-l12-l13-l14"),
- RPMH_VREG("ldo13", "ldo%s13", &pmic4_pldo_lv, "vdd-l8-l9-l10-l11-l12-l13-l14"),
- RPMH_VREG("ldo14", "ldo%s14", &pmic4_pldo_lv, "vdd-l8-l9-l10-l11-l12-l13-l14"),
- RPMH_VREG("ldo15", "ldo%s15", &pmic4_pldo, "vdd-l15-l16-l17-l18-l19"),
- RPMH_VREG("ldo16", "ldo%s16", &pmic4_pldo, "vdd-l15-l16-l17-l18-l19"),
- RPMH_VREG("ldo17", "ldo%s17", &pmic4_pldo, "vdd-l15-l16-l17-l18-l19"),
- RPMH_VREG("ldo18", "ldo%s18", &pmic4_pldo, "vdd-l15-l16-l17-l18-l19"),
- RPMH_VREG("ldo19", "ldo%s19", &pmic4_pldo, "vdd-l15-l16-l17-l18-l19"),
+ RPMH_VREG("ldo5", LDO, 5, &pmic4_nldo, "vdd-l5"),
+ RPMH_VREG("ldo6", LDO, 6, &pmic4_nldo, "vdd-l1-l6-l7"),
+ RPMH_VREG("ldo7", LDO, 7, &pmic4_nldo, "vdd-l1-l6-l7"),
+ RPMH_VREG("ldo8", LDO, 8, &pmic4_pldo_lv, "vdd-l8-l9-l10-l11-l12-l13-l14"),
+ RPMH_VREG("ldo9", LDO, 9, &pmic4_pldo_lv, "vdd-l8-l9-l10-l11-l12-l13-l14"),
+ RPMH_VREG("ldo10", LDO, 10, &pmic4_pldo_lv, "vdd-l8-l9-l10-l11-l12-l13-l14"),
+ RPMH_VREG("ldo11", LDO, 11, &pmic4_pldo_lv, "vdd-l8-l9-l10-l11-l12-l13-l14"),
+ RPMH_VREG("ldo12", LDO, 12, &pmic4_pldo_lv, "vdd-l8-l9-l10-l11-l12-l13-l14"),
+ RPMH_VREG("ldo13", LDO, 13, &pmic4_pldo_lv, "vdd-l8-l9-l10-l11-l12-l13-l14"),
+ RPMH_VREG("ldo14", LDO, 14, &pmic4_pldo_lv, "vdd-l8-l9-l10-l11-l12-l13-l14"),
+ RPMH_VREG("ldo15", LDO, 15, &pmic4_pldo, "vdd-l15-l16-l17-l18-l19"),
+ RPMH_VREG("ldo16", LDO, 16, &pmic4_pldo, "vdd-l15-l16-l17-l18-l19"),
+ RPMH_VREG("ldo17", LDO, 17, &pmic4_pldo, "vdd-l15-l16-l17-l18-l19"),
+ RPMH_VREG("ldo18", LDO, 18, &pmic4_pldo, "vdd-l15-l16-l17-l18-l19"),
+ RPMH_VREG("ldo19", LDO, 19, &pmic4_pldo, "vdd-l15-l16-l17-l18-l19"),
{}
};
static const struct rpmh_vreg_init_data pm660l_vreg_data[] = {
- RPMH_VREG("smps1", "smp%s1", &pmic4_ftsmps426, "vdd-s1"),
- RPMH_VREG("smps2", "smp%s2", &pmic4_ftsmps426, "vdd-s2"),
- RPMH_VREG("smps3", "smp%s3", &pmic4_ftsmps426, "vdd-s3-s4"),
- RPMH_VREG("smps5", "smp%s5", &pmic4_ftsmps426, "vdd-s5"),
- RPMH_VREG("ldo1", "ldo%s1", &pmic4_nldo, "vdd-l1-l9-l10"),
- RPMH_VREG("ldo2", "ldo%s2", &pmic4_pldo, "vdd-l2"),
- RPMH_VREG("ldo3", "ldo%s3", &pmic4_pldo, "vdd-l3-l5-l7-l8"),
- RPMH_VREG("ldo4", "ldo%s4", &pmic4_pldo, "vdd-l4-l6"),
- RPMH_VREG("ldo5", "ldo%s5", &pmic4_pldo, "vdd-l3-l5-l7-l8"),
- RPMH_VREG("ldo6", "ldo%s6", &pmic4_pldo, "vdd-l4-l6"),
- RPMH_VREG("ldo7", "ldo%s7", &pmic4_pldo, "vdd-l3-l5-l7-l8"),
- RPMH_VREG("ldo8", "ldo%s8", &pmic4_pldo, "vdd-l3-l5-l7-l8"),
- RPMH_VREG("bob", "bob%s1", &pmic4_bob, "vdd-bob"),
+ RPMH_VREG("smps1", SMPS, 1, &pmic4_ftsmps426, "vdd-s1"),
+ RPMH_VREG("smps2", SMPS, 2, &pmic4_ftsmps426, "vdd-s2"),
+ RPMH_VREG("smps3", SMPS, 3, &pmic4_ftsmps426, "vdd-s3-s4"),
+ RPMH_VREG("smps5", SMPS, 5, &pmic4_ftsmps426, "vdd-s5"),
+ RPMH_VREG("ldo1", LDO, 1, &pmic4_nldo, "vdd-l1-l9-l10"),
+ RPMH_VREG("ldo2", LDO, 2, &pmic4_pldo, "vdd-l2"),
+ RPMH_VREG("ldo3", LDO, 3, &pmic4_pldo, "vdd-l3-l5-l7-l8"),
+ RPMH_VREG("ldo4", LDO, 4, &pmic4_pldo, "vdd-l4-l6"),
+ RPMH_VREG("ldo5", LDO, 5, &pmic4_pldo, "vdd-l3-l5-l7-l8"),
+ RPMH_VREG("ldo6", LDO, 6, &pmic4_pldo, "vdd-l4-l6"),
+ RPMH_VREG("ldo7", LDO, 7, &pmic4_pldo, "vdd-l3-l5-l7-l8"),
+ RPMH_VREG("ldo8", LDO, 8, &pmic4_pldo, "vdd-l3-l5-l7-l8"),
+ RPMH_VREG("bob", BOB, 1, &pmic4_bob, "vdd-bob"),
{}
};
--
2.25.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 4/4] regulator: rpmh-regulator: Add RPMH regulator support for Glymur
2025-09-16 12:58 [PATCH v2 0/4] rpmh-regulators: Update rpmh-regulator driver and dt-bindings for Glymur Kamal Wadhwa
` (2 preceding siblings ...)
2025-09-16 12:58 ` [PATCH v2 3/4] regulator: rpmh-regulator: Add support for new resource name format Kamal Wadhwa
@ 2025-09-16 12:58 ` Kamal Wadhwa
3 siblings, 0 replies; 7+ messages in thread
From: Kamal Wadhwa @ 2025-09-16 12:58 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, dmitry.baryshkov, konrad.dybcio
Cc: linux-arm-msm, Krzysztof Kozlowski, linux-kernel, devicetree,
Kamal Wadhwa, jishnu.prakash
Add support for PMH0101/PMCX0102/PMH0110/PMH0104 PMIC voltage
regulators which are present on Glymur boards.
Introduce new LDOs & SMPSs under them (PMIC5 subtype 530 for
both).
For these new LDOs support a new optimum power mode(OPM). In
this mode LDO will automatically switch between high power mode
(HPM) and low power mode (LPM) based on the real-time LDO load
current. Its operation is analogous to SMPS AUTO mode.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Co-developed-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
---
drivers/regulator/qcom-rpmh-regulator.c | 188 +++++++++++++++++++++++++++++++-
1 file changed, 187 insertions(+), 1 deletion(-)
diff --git a/drivers/regulator/qcom-rpmh-regulator.c b/drivers/regulator/qcom-rpmh-regulator.c
index 525904956705cbb94a5abb63fb050eb967de4109..52e5499453b6931b6ab2e7aaa4bdba1978c4d69d 100644
--- a/drivers/regulator/qcom-rpmh-regulator.c
+++ b/drivers/regulator/qcom-rpmh-regulator.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
-// Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+// Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
#define pr_fmt(fmt) "%s: " fmt, __func__
@@ -91,6 +91,11 @@ static const struct resource_name_formats vreg_rsc_name_lookup[NUM_REGULATOR_TYP
#define PMIC5_BOB_MODE_AUTO 6
#define PMIC5_BOB_MODE_PWM 7
+#define PMIC530_LDO_MODE_RETENTION 3
+#define PMIC530_LDO_MODE_LPM 4
+#define PMIC530_LDO_MODE_OPM 5
+#define PMIC530_LDO_MODE_HPM 7
+
#define PMIC_ID_LEN 4
/**
* struct rpmh_vreg_hw_data - RPMh regulator hardware configurations
@@ -556,6 +561,14 @@ static const int pmic_mode_map_pmic5_ldo_hpm[REGULATOR_MODE_STANDBY + 1] = {
[REGULATOR_MODE_FAST] = -EINVAL,
};
+static const int pmic_mode_map_pmic530_ldo[REGULATOR_MODE_STANDBY + 1] = {
+ [REGULATOR_MODE_INVALID] = -EINVAL,
+ [REGULATOR_MODE_STANDBY] = PMIC530_LDO_MODE_RETENTION,
+ [REGULATOR_MODE_IDLE] = PMIC530_LDO_MODE_LPM,
+ [REGULATOR_MODE_NORMAL] = PMIC530_LDO_MODE_OPM,
+ [REGULATOR_MODE_FAST] = PMIC530_LDO_MODE_HPM,
+};
+
static unsigned int rpmh_regulator_pmic4_ldo_of_map_mode(unsigned int rpmh_mode)
{
unsigned int mode;
@@ -578,6 +591,30 @@ static unsigned int rpmh_regulator_pmic4_ldo_of_map_mode(unsigned int rpmh_mode)
return mode;
}
+static unsigned int rpmh_regulator_pmic530_ldo_of_map_mode(unsigned int rpmh_mode)
+{
+ unsigned int mode;
+
+ switch (rpmh_mode) {
+ case RPMH_REGULATOR_MODE_HPM:
+ mode = REGULATOR_MODE_FAST;
+ break;
+ case RPMH_REGULATOR_MODE_AUTO:
+ mode = REGULATOR_MODE_NORMAL;
+ break;
+ case RPMH_REGULATOR_MODE_LPM:
+ mode = REGULATOR_MODE_IDLE;
+ break;
+ case RPMH_REGULATOR_MODE_RET:
+ mode = REGULATOR_MODE_STANDBY;
+ break;
+ default:
+ mode = REGULATOR_MODE_INVALID;
+ break;
+ }
+ return mode;
+}
+
static const int pmic_mode_map_pmic4_smps[REGULATOR_MODE_STANDBY + 1] = {
[REGULATOR_MODE_INVALID] = -EINVAL,
[REGULATOR_MODE_STANDBY] = PMIC4_SMPS_MODE_RETENTION,
@@ -941,6 +978,71 @@ static const struct rpmh_vreg_hw_data pmic5_bob = {
.of_map_mode = rpmh_regulator_pmic4_bob_of_map_mode,
};
+static const struct rpmh_vreg_hw_data pmic5_nldo530 = {
+ .regulator_type = VRM,
+ .ops = &rpmh_regulator_vrm_drms_ops,
+ .voltage_ranges = (struct linear_range[]) {
+ REGULATOR_LINEAR_RANGE(320000, 0, 210, 8000),
+ },
+ .n_linear_ranges = 1,
+ .n_voltages = 211,
+ .hpm_min_load_uA = 30000,
+ .pmic_mode_map = pmic_mode_map_pmic530_ldo,
+ .of_map_mode = rpmh_regulator_pmic530_ldo_of_map_mode,
+};
+
+static const struct rpmh_vreg_hw_data pmic5_pldo530_mvp150 = {
+ .regulator_type = VRM,
+ .ops = &rpmh_regulator_vrm_drms_ops,
+ .voltage_ranges = (struct linear_range[]) {
+ REGULATOR_LINEAR_RANGE(1504000, 0, 255, 8000),
+ },
+ .n_linear_ranges = 1,
+ .n_voltages = 256,
+ .hpm_min_load_uA = 10000,
+ .pmic_mode_map = pmic_mode_map_pmic530_ldo,
+ .of_map_mode = rpmh_regulator_pmic530_ldo_of_map_mode,
+};
+
+static const struct rpmh_vreg_hw_data pmic5_pldo530_mvp300 = {
+ .regulator_type = VRM,
+ .ops = &rpmh_regulator_vrm_drms_ops,
+ .voltage_ranges = (struct linear_range[]) {
+ REGULATOR_LINEAR_RANGE(1504000, 0, 255, 8000),
+ },
+ .n_linear_ranges = 1,
+ .n_voltages = 256,
+ .hpm_min_load_uA = 20000,
+ .pmic_mode_map = pmic_mode_map_pmic530_ldo,
+ .of_map_mode = rpmh_regulator_pmic530_ldo_of_map_mode,
+};
+
+static const struct rpmh_vreg_hw_data pmic5_pldo530_mvp600 = {
+ .regulator_type = VRM,
+ .ops = &rpmh_regulator_vrm_drms_ops,
+ .voltage_ranges = (struct linear_range[]) {
+ REGULATOR_LINEAR_RANGE(1504000, 0, 255, 8000),
+ },
+ .n_linear_ranges = 1,
+ .n_voltages = 256,
+ .hpm_min_load_uA = 40000,
+ .pmic_mode_map = pmic_mode_map_pmic530_ldo,
+ .of_map_mode = rpmh_regulator_pmic530_ldo_of_map_mode,
+};
+
+static const struct rpmh_vreg_hw_data pmic5_ftsmps530 = {
+ .regulator_type = VRM,
+ .ops = &rpmh_regulator_vrm_ops,
+ .voltage_ranges = (struct linear_range[]) {
+ REGULATOR_LINEAR_RANGE(252000, 0, 305, 4000),
+ REGULATOR_LINEAR_RANGE(1480000, 306, 464, 8000),
+ },
+ .n_linear_ranges = 2,
+ .n_voltages = 465,
+ .pmic_mode_map = pmic_mode_map_pmic5_smps,
+ .of_map_mode = rpmh_regulator_pmic4_smps_of_map_mode,
+};
+
#define RPMH_VREG(_name, _vreg_hw_type, _index, _hw_data, _supply_name) \
{ \
.name = _name, \
@@ -1375,6 +1477,74 @@ static const struct rpmh_vreg_init_data pm6350_vreg_data[] = {
RPMH_VREG("ldo22", LDO, 22, &pmic5_nldo, NULL),
};
+static const struct rpmh_vreg_init_data pmcx0102_vreg_data[] = {
+ RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps530, "vdd-s1"),
+ RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps530, "vdd-s2"),
+ RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps530, "vdd-s3"),
+ RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps530, "vdd-s4"),
+ RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps530, "vdd-s5"),
+ RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps530, "vdd-s6"),
+ RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps530, "vdd-s7"),
+ RPMH_VREG("smps8", SMPS, 8, &pmic5_ftsmps530, "vdd-s8"),
+ RPMH_VREG("smps9", SMPS, 9, &pmic5_ftsmps530, "vdd-s9"),
+ RPMH_VREG("smps10", SMPS, 10, &pmic5_ftsmps530, "vdd-s10"),
+ RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo530, "vdd-l1"),
+ RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo530, "vdd-l2"),
+ RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo530, "vdd-l3"),
+ RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo530, "vdd-l4"),
+ {}
+};
+
+static const struct rpmh_vreg_init_data pmh0101_vreg_data[] = {
+ RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo530, "vdd-l1-l4-l10"),
+ RPMH_VREG("ldo2", LDO, 2, &pmic5_pldo530_mvp300, "vdd-l2-l13-l14"),
+ RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo530, "vdd-l3-l11"),
+ RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo530, "vdd-l1-l4-l10"),
+ RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo530_mvp150, "vdd-l5-l16"),
+ RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo530_mvp300, "vdd-l6-l7"),
+ RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo530_mvp300, "vdd-l6-l7"),
+ RPMH_VREG("ldo8", LDO, 8, &pmic5_pldo530_mvp150, "vdd-l8-l9"),
+ RPMH_VREG("ldo9", LDO, 9, &pmic5_pldo515_mv, "vdd-l8-l9"),
+ RPMH_VREG("ldo10", LDO, 10, &pmic5_nldo530, "vdd-l1-l4-l10"),
+ RPMH_VREG("ldo11", LDO, 11, &pmic5_nldo530, "vdd-l3-l11"),
+ RPMH_VREG("ldo12", LDO, 12, &pmic5_nldo530, "vdd-l12"),
+ RPMH_VREG("ldo13", LDO, 13, &pmic5_pldo530_mvp150, "vdd-l2-l13-l14"),
+ RPMH_VREG("ldo14", LDO, 14, &pmic5_pldo530_mvp150, "vdd-l2-l13-l14"),
+ RPMH_VREG("ldo15", LDO, 15, &pmic5_nldo530, "vdd-l15"),
+ RPMH_VREG("ldo16", LDO, 15, &pmic5_pldo530_mvp600, "vdd-l5-l16"),
+ RPMH_VREG("ldo17", LDO, 17, &pmic5_pldo515_mv, "vdd-l17"),
+ RPMH_VREG("ldo18", LDO, 18, &pmic5_nldo530, "vdd-l18"),
+ RPMH_VREG("bob1", BOB, 1, &pmic5_bob, "vdd-bob1"),
+ RPMH_VREG("bob2", BOB, 2, &pmic5_bob, "vdd-bob2"),
+ {}
+};
+
+static const struct rpmh_vreg_init_data pmh0104_vreg_data[] = {
+ RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps530, "vdd-s1"),
+ RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps530, "vdd-s2"),
+ RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps530, "vdd-s3"),
+ RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps530, "vdd-s4"),
+ {}
+};
+
+static const struct rpmh_vreg_init_data pmh0110_vreg_data[] = {
+ RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps530, "vdd-s1"),
+ RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps530, "vdd-s2"),
+ RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps530, "vdd-s3"),
+ RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps530, "vdd-s4"),
+ RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps530, "vdd-s5"),
+ RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps530, "vdd-s6"),
+ RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps530, "vdd-s7"),
+ RPMH_VREG("smps8", SMPS, 8, &pmic5_ftsmps530, "vdd-s8"),
+ RPMH_VREG("smps9", SMPS, 9, &pmic5_ftsmps530, "vdd-s9"),
+ RPMH_VREG("smps10", SMPS, 10, &pmic5_ftsmps530, "vdd-s10"),
+ RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo530, "vdd-l1"),
+ RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo530, "vdd-l2"),
+ RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo530, "vdd-l3"),
+ RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo530, "vdd-l4"),
+ {}
+};
+
static const struct rpmh_vreg_init_data pmx55_vreg_data[] = {
RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps510, "vdd-s1"),
RPMH_VREG("smps2", SMPS, 2, &pmic5_hfsmps510, "vdd-s2"),
@@ -1727,6 +1897,22 @@ static const struct of_device_id __maybe_unused rpmh_regulator_match_table[] = {
.compatible = "qcom,pmc8380-rpmh-regulators",
.data = pmc8380_vreg_data,
},
+ {
+ .compatible = "qcom,pmcx0102-rpmh-regulators",
+ .data = pmcx0102_vreg_data,
+ },
+ {
+ .compatible = "qcom,pmh0101-rpmh-regulators",
+ .data = pmh0101_vreg_data,
+ },
+ {
+ .compatible = "qcom,pmh0104-rpmh-regulators",
+ .data = pmh0104_vreg_data,
+ },
+ {
+ .compatible = "qcom,pmh0110-rpmh-regulators",
+ .data = pmh0110_vreg_data,
+ },
{
.compatible = "qcom,pmm8155au-rpmh-regulators",
.data = pmm8155au_vreg_data,
--
2.25.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 2/4] dt-bindings: rpmh-regulator: Update pmic-id property description
2025-09-16 12:58 ` [PATCH v2 2/4] dt-bindings: rpmh-regulator: Update pmic-id property description Kamal Wadhwa
@ 2025-09-16 15:08 ` Dmitry Baryshkov
0 siblings, 0 replies; 7+ messages in thread
From: Dmitry Baryshkov @ 2025-09-16 15:08 UTC (permalink / raw)
To: Kamal Wadhwa
Cc: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, konrad.dybcio, linux-arm-msm,
Krzysztof Kozlowski, linux-kernel, devicetree, jishnu.prakash
On Tue, Sep 16, 2025 at 06:28:53PM +0530, Kamal Wadhwa wrote:
> The `pmic-id` property previously accepted a single lowercase alphabet
> in the range [a-n]. However, on new targets such as Glymur, the
> property uses a new format: `[A-N]_E[0-3]`, where `[A-N]` represents
> the PMIC ID and `[0-3]` represents the BUS ID.
You are sstating that the property uses a different format. Instead you
should write that on these platforms there are multiple SPMI bus in use,
so pmic-id needs to specify both PMIC 'letter' and bus ID. The proposed
format follows the cmd-db format.
>
> Update the property description to reflect this new pattern format,
> matching the updated driver implementation.
>
> Note - Old format [a-n] is still valid and will work for existing
> targets.
>
> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> ---
> Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml b/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml
> index 40e57b10ebbebeff130871b6d978df64111b6f29..40ddc64577e78b5c0dbb7b4e8893a08e8b37c92e 100644
> --- a/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml
> +++ b/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml
> @@ -108,7 +108,7 @@ properties:
> RPMh resource name suffix used for the regulators found
> on this PMIC.
> $ref: /schemas/types.yaml#/definitions/string
> - enum: [a, b, c, d, e, f, g, h, i, j, k, l, m, n]
> + pattern: "^[a-n]|[A-N]_E[0-3]+$"
>
> qcom,always-wait-for-ack:
> description: |
>
> --
> 2.25.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 3/4] regulator: rpmh-regulator: Add support for new resource name format
2025-09-16 12:58 ` [PATCH v2 3/4] regulator: rpmh-regulator: Add support for new resource name format Kamal Wadhwa
@ 2025-09-17 11:05 ` kernel test robot
0 siblings, 0 replies; 7+ messages in thread
From: kernel test robot @ 2025-09-17 11:05 UTC (permalink / raw)
To: Kamal Wadhwa, Liam Girdwood, Mark Brown, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
dmitry.baryshkov, konrad.dybcio
Cc: oe-kbuild-all, linux-arm-msm, linux-kernel, devicetree,
Kamal Wadhwa, jishnu.prakash
Hi Kamal,
kernel test robot noticed the following build warnings:
[auto build test WARNING on c3067c2c38316c3ef013636c93daa285ee6aaa2e]
url: https://github.com/intel-lab-lkp/linux/commits/Kamal-Wadhwa/dt-bindings-rpmh-regulator-Add-compatibles-for-PMH01XX-PMCX0102/20250916-210231
base: c3067c2c38316c3ef013636c93daa285ee6aaa2e
patch link: https://lore.kernel.org/r/20250916-glymur-rpmh-regulator-driver-v2-3-c6593ff9b4be%40oss.qualcomm.com
patch subject: [PATCH v2 3/4] regulator: rpmh-regulator: Add support for new resource name format
config: i386-buildonly-randconfig-001-20250917 (https://download.01.org/0day-ci/archive/20250917/202509171822.oRjF64pS-lkp@intel.com/config)
compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250917/202509171822.oRjF64pS-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202509171822.oRjF64pS-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> Warning: drivers/regulator/qcom-rpmh-regulator.c:47 Enum value 'NUM_REGULATOR_TYPES' not described in enum 'regulator_hw_type'
>> Warning: drivers/regulator/qcom-rpmh-regulator.c:167 bad line: on the PMIC.
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2025-09-17 11:05 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2025-09-16 12:58 [PATCH v2 0/4] rpmh-regulators: Update rpmh-regulator driver and dt-bindings for Glymur Kamal Wadhwa
2025-09-16 12:58 ` [PATCH v2 1/4] dt-bindings: rpmh-regulator : Add compatibles for PMH01XX & PMCX0102 Kamal Wadhwa
2025-09-16 12:58 ` [PATCH v2 2/4] dt-bindings: rpmh-regulator: Update pmic-id property description Kamal Wadhwa
2025-09-16 15:08 ` Dmitry Baryshkov
2025-09-16 12:58 ` [PATCH v2 3/4] regulator: rpmh-regulator: Add support for new resource name format Kamal Wadhwa
2025-09-17 11:05 ` kernel test robot
2025-09-16 12:58 ` [PATCH v2 4/4] regulator: rpmh-regulator: Add RPMH regulator support for Glymur Kamal Wadhwa
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