[PATCH] riscv: Add pgprot_dmacoherent definition

[guoren@kernel.org]

From: "Guo Ren (Alibaba DAMO Academy)" <guoren@kernel.org>

RISC-V Svpbmt Standard Extension for Page-Based Memory Types
defines three modes:

 Mode | Value | Requested Memory Attributes
 PMA  |   0   | None
 NC   |   1   | Non-cacheable, idempotent, weakly-ordered (RVWMO),
      |       | main memory
 IO   |   2   | Non-cacheable, non-idempotent, strongly-ordered
      |       | (I/O ordering), I/O

The pgprot_dmacoherent default uses the IO memory attribute if there
is no asm definition, but IO is not for main memory according to
Svpbmt rules.

This commit corrects pgprot_dmacoherent with the NC memory attribute,
which satisfies performance improvement and prevents using the IO
attribute to access main memory.

Signed-off-by: Guo Ren (Alibaba DAMO Academy) <guoren@kernel.org>
---
 arch/riscv/include/asm/pgtable.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 29e994a9afb6..2a84479de81b 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -654,6 +654,15 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
 	return __pgprot(prot);
 }
 
+/*
+ * DMA allocations for non-coherent devices use what the RISC-V architecture
+ * call "Non-Cacheable" memory attribute, which permits idempotent, weakly-ordered
+ * (RVWMO), main memory. This is different from "I/O" memory attribute which is
+ * intended for MMIO access with Non-cacheable, non-idempotent, strongly-ordered
+ * (I/O ordering), I/O attributes.
+ */
+#define pgprot_dmacoherent pgprot_writecombine
+
 /*
  * Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By
  * default the M-mode firmware enables the hardware updating scheme when only Svadu is present in
-- 
2.40.1