* [PATCH] riscv: Add pgprot_dmacoherent definition
@ 2025-10-11 15:57 guoren
2025-10-12 6:11 ` Guo Ren
2025-10-12 15:51 ` Anup Patel
0 siblings, 2 replies; 6+ messages in thread
From: guoren @ 2025-10-11 15:57 UTC (permalink / raw)
To: samuel.holland, david, yongxuan.wang, cuiyunhui, luxu.kernel
Cc: guoren, paul.walmsley, aou, alex, palmer, linux-riscv, linux-kernel
From: "Guo Ren (Alibaba DAMO Academy)" <guoren@kernel.org>
RISC-V Svpbmt Standard Extension for Page-Based Memory Types
defines three modes:
Mode | Value | Requested Memory Attributes
PMA | 0 | None
NC | 1 | Non-cacheable, idempotent, weakly-ordered (RVWMO),
| | main memory
IO | 2 | Non-cacheable, non-idempotent, strongly-ordered
| | (I/O ordering), I/O
The pgprot_dmacoherent default uses the IO memory attribute if there
is no asm definition, but IO is not for main memory according to
Svpbmt rules.
This commit corrects pgprot_dmacoherent with the NC memory attribute,
which satisfies performance improvement and prevents using the IO
attribute to access main memory.
Signed-off-by: Guo Ren (Alibaba DAMO Academy) <guoren@kernel.org>
---
arch/riscv/include/asm/pgtable.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 29e994a9afb6..2a84479de81b 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -654,6 +654,15 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
return __pgprot(prot);
}
+/*
+ * DMA allocations for non-coherent devices use what the RISC-V architecture
+ * call "Non-Cacheable" memory attribute, which permits idempotent, weakly-ordered
+ * (RVWMO), main memory. This is different from "I/O" memory attribute which is
+ * intended for MMIO access with Non-cacheable, non-idempotent, strongly-ordered
+ * (I/O ordering), I/O attributes.
+ */
+#define pgprot_dmacoherent pgprot_writecombine
+
/*
* Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By
* default the M-mode firmware enables the hardware updating scheme when only Svadu is present in
--
2.40.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: Add pgprot_dmacoherent definition
2025-10-11 15:57 [PATCH] riscv: Add pgprot_dmacoherent definition guoren
@ 2025-10-12 6:11 ` Guo Ren
2025-10-12 15:51 ` Anup Patel
1 sibling, 0 replies; 6+ messages in thread
From: Guo Ren @ 2025-10-12 6:11 UTC (permalink / raw)
To: samuel.holland, david, yongxuan.wang, cuiyunhui, luxu.kernel
Cc: paul.walmsley, aou, alex, palmer, linux-riscv, linux-kernel
Anup's patch has solved this:
https://lore.kernel.org/linux-riscv/20250820152316.1012757-1-apatel@ventanamicro.com/
So, I abandon this patch.
On Sat, Oct 11, 2025 at 11:58 PM <guoren@kernel.org> wrote:
>
> From: "Guo Ren (Alibaba DAMO Academy)" <guoren@kernel.org>
>
> RISC-V Svpbmt Standard Extension for Page-Based Memory Types
> defines three modes:
>
> Mode | Value | Requested Memory Attributes
> PMA | 0 | None
> NC | 1 | Non-cacheable, idempotent, weakly-ordered (RVWMO),
> | | main memory
> IO | 2 | Non-cacheable, non-idempotent, strongly-ordered
> | | (I/O ordering), I/O
>
> The pgprot_dmacoherent default uses the IO memory attribute if there
> is no asm definition, but IO is not for main memory according to
> Svpbmt rules.
>
> This commit corrects pgprot_dmacoherent with the NC memory attribute,
> which satisfies performance improvement and prevents using the IO
> attribute to access main memory.
>
> Signed-off-by: Guo Ren (Alibaba DAMO Academy) <guoren@kernel.org>
> ---
> arch/riscv/include/asm/pgtable.h | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index 29e994a9afb6..2a84479de81b 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -654,6 +654,15 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
> return __pgprot(prot);
> }
>
> +/*
> + * DMA allocations for non-coherent devices use what the RISC-V architecture
> + * call "Non-Cacheable" memory attribute, which permits idempotent, weakly-ordered
> + * (RVWMO), main memory. This is different from "I/O" memory attribute which is
> + * intended for MMIO access with Non-cacheable, non-idempotent, strongly-ordered
> + * (I/O ordering), I/O attributes.
> + */
> +#define pgprot_dmacoherent pgprot_writecombine
> +
> /*
> * Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By
> * default the M-mode firmware enables the hardware updating scheme when only Svadu is present in
> --
> 2.40.1
>
--
Best Regards
Guo Ren
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: Add pgprot_dmacoherent definition
2025-10-11 15:57 [PATCH] riscv: Add pgprot_dmacoherent definition guoren
2025-10-12 6:11 ` Guo Ren
@ 2025-10-12 15:51 ` Anup Patel
2025-10-12 23:50 ` Guo Ren
1 sibling, 1 reply; 6+ messages in thread
From: Anup Patel @ 2025-10-12 15:51 UTC (permalink / raw)
To: guoren
Cc: samuel.holland, david, yongxuan.wang, cuiyunhui, luxu.kernel,
paul.walmsley, aou, alex, palmer, linux-riscv, linux-kernel
On Sat, Oct 11, 2025 at 9:28 PM <guoren@kernel.org> wrote:
>
> From: "Guo Ren (Alibaba DAMO Academy)" <guoren@kernel.org>
>
> RISC-V Svpbmt Standard Extension for Page-Based Memory Types
> defines three modes:
>
> Mode | Value | Requested Memory Attributes
> PMA | 0 | None
> NC | 1 | Non-cacheable, idempotent, weakly-ordered (RVWMO),
> | | main memory
> IO | 2 | Non-cacheable, non-idempotent, strongly-ordered
> | | (I/O ordering), I/O
>
> The pgprot_dmacoherent default uses the IO memory attribute if there
> is no asm definition, but IO is not for main memory according to
> Svpbmt rules.
>
> This commit corrects pgprot_dmacoherent with the NC memory attribute,
> which satisfies performance improvement and prevents using the IO
> attribute to access main memory.
>
> Signed-off-by: Guo Ren (Alibaba DAMO Academy) <guoren@kernel.org>
I had sent the same patch on Aug 20 and you had provided
Tested-by to that patch.
If you had concerns with my patch then you could have provided
comments but you choose to hijack it and change authorship.
Regards,
Anup
> ---
> arch/riscv/include/asm/pgtable.h | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index 29e994a9afb6..2a84479de81b 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -654,6 +654,15 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
> return __pgprot(prot);
> }
>
> +/*
> + * DMA allocations for non-coherent devices use what the RISC-V architecture
> + * call "Non-Cacheable" memory attribute, which permits idempotent, weakly-ordered
> + * (RVWMO), main memory. This is different from "I/O" memory attribute which is
> + * intended for MMIO access with Non-cacheable, non-idempotent, strongly-ordered
> + * (I/O ordering), I/O attributes.
> + */
> +#define pgprot_dmacoherent pgprot_writecombine
> +
> /*
> * Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By
> * default the M-mode firmware enables the hardware updating scheme when only Svadu is present in
> --
> 2.40.1
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: Add pgprot_dmacoherent definition
2025-10-12 15:51 ` Anup Patel
@ 2025-10-12 23:50 ` Guo Ren
2025-10-13 0:29 ` Guo Ren
0 siblings, 1 reply; 6+ messages in thread
From: Guo Ren @ 2025-10-12 23:50 UTC (permalink / raw)
To: Anup Patel
Cc: samuel.holland, david, yongxuan.wang, cuiyunhui, luxu.kernel,
paul.walmsley, aou, alex, palmer, linux-riscv, linux-kernel
On Sun, Oct 12, 2025 at 11:51 PM Anup Patel <apatel@ventanamicro.com> wrote:
>
> On Sat, Oct 11, 2025 at 9:28 PM <guoren@kernel.org> wrote:
> >
> > From: "Guo Ren (Alibaba DAMO Academy)" <guoren@kernel.org>
> >
> > RISC-V Svpbmt Standard Extension for Page-Based Memory Types
> > defines three modes:
> >
> > Mode | Value | Requested Memory Attributes
> > PMA | 0 | None
> > NC | 1 | Non-cacheable, idempotent, weakly-ordered (RVWMO),
> > | | main memory
> > IO | 2 | Non-cacheable, non-idempotent, strongly-ordered
> > | | (I/O ordering), I/O
> >
> > The pgprot_dmacoherent default uses the IO memory attribute if there
> > is no asm definition, but IO is not for main memory according to
> > Svpbmt rules.
> >
> > This commit corrects pgprot_dmacoherent with the NC memory attribute,
> > which satisfies performance improvement and prevents using the IO
> > attribute to access main memory.
> >
> > Signed-off-by: Guo Ren (Alibaba DAMO Academy) <guoren@kernel.org>
>
> I had sent the same patch on Aug 20 and you had provided
> Tested-by to that patch.
>
> If you had concerns with my patch then you could have provided
> comments but you choose to hijack it and change authorship.
I didn't find your patch at first, so I sent it out. When I discovered
your patch, I gave the Tested-by to yours.
I've added the abandoned reply to this thread. Have you seen that [1]?
[1] https://lore.kernel.org/all/CAJF2gTRfLzrqHoYrexS55AT3sjn5VbbNKf2WMEGWrw9ERRLYYA@mail.gmail.com/
>
> Regards,
> Anup
>
> > ---
> > arch/riscv/include/asm/pgtable.h | 9 +++++++++
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> > index 29e994a9afb6..2a84479de81b 100644
> > --- a/arch/riscv/include/asm/pgtable.h
> > +++ b/arch/riscv/include/asm/pgtable.h
> > @@ -654,6 +654,15 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
> > return __pgprot(prot);
> > }
> >
> > +/*
> > + * DMA allocations for non-coherent devices use what the RISC-V architecture
> > + * call "Non-Cacheable" memory attribute, which permits idempotent, weakly-ordered
> > + * (RVWMO), main memory. This is different from "I/O" memory attribute which is
> > + * intended for MMIO access with Non-cacheable, non-idempotent, strongly-ordered
> > + * (I/O ordering), I/O attributes.
> > + */
> > +#define pgprot_dmacoherent pgprot_writecombine
> > +
> > /*
> > * Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By
> > * default the M-mode firmware enables the hardware updating scheme when only Svadu is present in
> > --
> > 2.40.1
> >
> >
--
Best Regards
Guo Ren
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: Add pgprot_dmacoherent definition
2025-10-12 23:50 ` Guo Ren
@ 2025-10-13 0:29 ` Guo Ren
2025-10-13 3:39 ` Anup Patel
0 siblings, 1 reply; 6+ messages in thread
From: Guo Ren @ 2025-10-13 0:29 UTC (permalink / raw)
To: Anup Patel
Cc: samuel.holland, david, yongxuan.wang, cuiyunhui, luxu.kernel,
paul.walmsley, aou, alex, palmer, linux-riscv, linux-kernel
On Mon, Oct 13, 2025 at 7:50 AM Guo Ren <guoren@kernel.org> wrote:
>
> On Sun, Oct 12, 2025 at 11:51 PM Anup Patel <apatel@ventanamicro.com> wrote:
> >
> > On Sat, Oct 11, 2025 at 9:28 PM <guoren@kernel.org> wrote:
> > >
> > > From: "Guo Ren (Alibaba DAMO Academy)" <guoren@kernel.org>
> > >
> > > RISC-V Svpbmt Standard Extension for Page-Based Memory Types
> > > defines three modes:
> > >
> > > Mode | Value | Requested Memory Attributes
> > > PMA | 0 | None
> > > NC | 1 | Non-cacheable, idempotent, weakly-ordered (RVWMO),
> > > | | main memory
> > > IO | 2 | Non-cacheable, non-idempotent, strongly-ordered
> > > | | (I/O ordering), I/O
> > >
> > > The pgprot_dmacoherent default uses the IO memory attribute if there
> > > is no asm definition, but IO is not for main memory according to
> > > Svpbmt rules.
> > >
> > > This commit corrects pgprot_dmacoherent with the NC memory attribute,
> > > which satisfies performance improvement and prevents using the IO
> > > attribute to access main memory.
> > >
> > > Signed-off-by: Guo Ren (Alibaba DAMO Academy) <guoren@kernel.org>
> >
> > I had sent the same patch on Aug 20 and you had provided
> > Tested-by to that patch.
> >
> > If you had concerns with my patch then you could have provided
> > comments but you choose to hijack it and change authorship.
> I didn't find your patch at first, so I sent it out. When I discovered
> your patch, I gave the Tested-by to yours.
> I've added the abandoned reply to this thread. Have you seen that [1]?
>
> [1] https://lore.kernel.org/all/CAJF2gTRfLzrqHoYrexS55AT3sjn5VbbNKf2WMEGWrw9ERRLYYA@mail.gmail.com/
This patch is on Sat, Oct 11, 2025 [1]
Guo's Tested-by is on Sun, 12 Oct 2025 02:07:34 [2]
Abandon reply is on Sun, 12 Oct 2025 14:11:42 [3]
Gao's Tested-by is on Sun, 12 Oct 2025 18:00:36 [4]
[1]: https://lore.kernel.org/all/20251011155746.1558731-1-guoren@kernel.org/
[2]: https://lore.kernel.org/linux-riscv/aOtR39pl5xjyYHn1@gmail.com/
[3]: https://lore.kernel.org/all/CAJF2gTRfLzrqHoYrexS55AT3sjn5VbbNKf2WMEGWrw9ERRLYYA@mail.gmail.com/
[4]: https://lore.kernel.org/linux-riscv/031395FE-C51C-45A7-85A3-CC4A25EB6066@gmail.com/
I also asked Gao to notice your patch and give it the Tested-by tag.
That's why you got two Tested-by on Oct 12 after two months. So, your
reply, "but you choose to hijack it and change authorship," makes me
sad.
Anyway, it's a vital fixup patch that resolved the bug that had
existed for many years of svpbmt, and I hope this misunderstanding can
draw the maintainers' attention and gain more Tested-by tags.
>
> >
> > Regards,
> > Anup
> >
> > > ---
> > > arch/riscv/include/asm/pgtable.h | 9 +++++++++
> > > 1 file changed, 9 insertions(+)
> > >
> > > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> > > index 29e994a9afb6..2a84479de81b 100644
> > > --- a/arch/riscv/include/asm/pgtable.h
> > > +++ b/arch/riscv/include/asm/pgtable.h
> > > @@ -654,6 +654,15 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
> > > return __pgprot(prot);
> > > }
> > >
> > > +/*
> > > + * DMA allocations for non-coherent devices use what the RISC-V architecture
> > > + * call "Non-Cacheable" memory attribute, which permits idempotent, weakly-ordered
> > > + * (RVWMO), main memory. This is different from "I/O" memory attribute which is
> > > + * intended for MMIO access with Non-cacheable, non-idempotent, strongly-ordered
> > > + * (I/O ordering), I/O attributes.
> > > + */
> > > +#define pgprot_dmacoherent pgprot_writecombine
> > > +
> > > /*
> > > * Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By
> > > * default the M-mode firmware enables the hardware updating scheme when only Svadu is present in
> > > --
> > > 2.40.1
> > >
> > >
>
>
>
> --
> Best Regards
> Guo Ren
--
Best Regards
Guo Ren
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: Add pgprot_dmacoherent definition
2025-10-13 0:29 ` Guo Ren
@ 2025-10-13 3:39 ` Anup Patel
0 siblings, 0 replies; 6+ messages in thread
From: Anup Patel @ 2025-10-13 3:39 UTC (permalink / raw)
To: Guo Ren
Cc: samuel.holland, david, yongxuan.wang, cuiyunhui, luxu.kernel,
paul.walmsley, aou, alex, palmer, linux-riscv, linux-kernel
On Mon, Oct 13, 2025 at 6:00 AM Guo Ren <guoren@kernel.org> wrote:
>
> On Mon, Oct 13, 2025 at 7:50 AM Guo Ren <guoren@kernel.org> wrote:
> >
> > On Sun, Oct 12, 2025 at 11:51 PM Anup Patel <apatel@ventanamicro.com> wrote:
> > >
> > > On Sat, Oct 11, 2025 at 9:28 PM <guoren@kernel.org> wrote:
> > > >
> > > > From: "Guo Ren (Alibaba DAMO Academy)" <guoren@kernel.org>
> > > >
> > > > RISC-V Svpbmt Standard Extension for Page-Based Memory Types
> > > > defines three modes:
> > > >
> > > > Mode | Value | Requested Memory Attributes
> > > > PMA | 0 | None
> > > > NC | 1 | Non-cacheable, idempotent, weakly-ordered (RVWMO),
> > > > | | main memory
> > > > IO | 2 | Non-cacheable, non-idempotent, strongly-ordered
> > > > | | (I/O ordering), I/O
> > > >
> > > > The pgprot_dmacoherent default uses the IO memory attribute if there
> > > > is no asm definition, but IO is not for main memory according to
> > > > Svpbmt rules.
> > > >
> > > > This commit corrects pgprot_dmacoherent with the NC memory attribute,
> > > > which satisfies performance improvement and prevents using the IO
> > > > attribute to access main memory.
> > > >
> > > > Signed-off-by: Guo Ren (Alibaba DAMO Academy) <guoren@kernel.org>
> > >
> > > I had sent the same patch on Aug 20 and you had provided
> > > Tested-by to that patch.
> > >
> > > If you had concerns with my patch then you could have provided
> > > comments but you choose to hijack it and change authorship.
> > I didn't find your patch at first, so I sent it out. When I discovered
> > your patch, I gave the Tested-by to yours.
> > I've added the abandoned reply to this thread. Have you seen that [1]?
> >
> > [1] https://lore.kernel.org/all/CAJF2gTRfLzrqHoYrexS55AT3sjn5VbbNKf2WMEGWrw9ERRLYYA@mail.gmail.com/
>
> This patch is on Sat, Oct 11, 2025 [1]
> Guo's Tested-by is on Sun, 12 Oct 2025 02:07:34 [2]
> Abandon reply is on Sun, 12 Oct 2025 14:11:42 [3]
> Gao's Tested-by is on Sun, 12 Oct 2025 18:00:36 [4]
>
> [1]: https://lore.kernel.org/all/20251011155746.1558731-1-guoren@kernel.org/
> [2]: https://lore.kernel.org/linux-riscv/aOtR39pl5xjyYHn1@gmail.com/
> [3]: https://lore.kernel.org/all/CAJF2gTRfLzrqHoYrexS55AT3sjn5VbbNKf2WMEGWrw9ERRLYYA@mail.gmail.com/
> [4]: https://lore.kernel.org/linux-riscv/031395FE-C51C-45A7-85A3-CC4A25EB6066@gmail.com/
>
> I also asked Gao to notice your patch and give it the Tested-by tag.
> That's why you got two Tested-by on Oct 12 after two months. So, your
> reply, "but you choose to hijack it and change authorship," makes me
> sad.
Please have better coordination among yourselves before
sending out patches.
It makes me sad when people blindly send patches without
noticing existing or on-going work. Sometimes it also happens
that people are already working on things which they have
announced in the appropriate RISE WG or RVI TG/SIG.
--
Anup
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-10-13 3:39 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2025-10-11 15:57 [PATCH] riscv: Add pgprot_dmacoherent definition guoren
2025-10-12 6:11 ` Guo Ren
2025-10-12 15:51 ` Anup Patel
2025-10-12 23:50 ` Guo Ren
2025-10-13 0:29 ` Guo Ren
2025-10-13 3:39 ` Anup Patel
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