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From: Alistair Popple <apopple@nvidia.com>
To: rust-for-linux@vger.kernel.org, dri-devel@lists.freedesktop.org,
	dakr@kernel.org, acourbot@nvidia.com
Cc: "Alistair Popple" <apopple@nvidia.com>,
	"Miguel Ojeda" <ojeda@kernel.org>,
	"Alex Gaynor" <alex.gaynor@gmail.com>,
	"Boqun Feng" <boqun.feng@gmail.com>,
	"Gary Guo" <gary@garyguo.net>,
	"Björn Roy Baron" <bjorn3_gh@protonmail.com>,
	"Benno Lossin" <lossin@kernel.org>,
	"Andreas Hindborg" <a.hindborg@kernel.org>,
	"Alice Ryhl" <aliceryhl@google.com>,
	"Trevor Gross" <tmgross@umich.edu>,
	"David Airlie" <airlied@gmail.com>,
	"Simona Vetter" <simona@ffwll.ch>,
	"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
	"Maxime Ripard" <mripard@kernel.org>,
	"Thomas Zimmermann" <tzimmermann@suse.de>,
	"John Hubbard" <jhubbard@nvidia.com>,
	"Joel Fernandes" <joelagnelf@nvidia.com>,
	"Timur Tabi" <ttabi@nvidia.com>,
	linux-kernel@vger.kernel.org, nouveau@lists.freedesktop.org
Subject: [PATCH v5 10/14] gpu: nova-core: Add bindings for the GSP RM registry tables
Date: Mon, 13 Oct 2025 17:20:36 +1100	[thread overview]
Message-ID: <20251013062041.1639529-11-apopple@nvidia.com> (raw)
In-Reply-To: <20251013062041.1639529-1-apopple@nvidia.com>

Adds bindings and constructors for PACKED_REGISTRY_TABLE and
PACKED_REGISTRY_ENTRY structures.

Signed-off-by: Alistair Popple <apopple@nvidia.com>

---

Changes for v5:
 - Derive Zeroable trait

Changes for v4:
 - Use `init!` macros
 - Add comments around only supporting DWORD entry types

Changes for v3:
 - New for v3
---
 drivers/gpu/nova-core/gsp/fw/commands.rs      | 49 +++++++++++++++++++
 .../gpu/nova-core/gsp/fw/r570_144/bindings.rs | 16 ++++++
 2 files changed, 65 insertions(+)

diff --git a/drivers/gpu/nova-core/gsp/fw/commands.rs b/drivers/gpu/nova-core/gsp/fw/commands.rs
index 9a524bba1ac4..79a69c6279e8 100644
--- a/drivers/gpu/nova-core/gsp/fw/commands.rs
+++ b/drivers/gpu/nova-core/gsp/fw/commands.rs
@@ -49,3 +49,52 @@ unsafe impl AsBytes for GspSystemInfo {}
 // SAFETY: These structs don't meet the no-padding requirements of FromBytes but
 //         that is not a problem because they are not used outside the kernel.
 unsafe impl FromBytes for GspSystemInfo {}
+
+#[repr(transparent)]
+pub(crate) struct PackedRegistryEntry(bindings::PACKED_REGISTRY_ENTRY);
+
+impl PackedRegistryEntry {
+    pub(crate) fn new(offset: u32, value: u32) -> Self {
+        Self({
+            bindings::PACKED_REGISTRY_ENTRY {
+                nameOffset: offset,
+
+                // We only support DWORD types for now. Support for other types
+                // will come later if required.
+                type_: bindings::REGISTRY_TABLE_ENTRY_TYPE_DWORD as u8,
+                __bindgen_padding_0: Default::default(),
+                data: value,
+                length: 0,
+            }
+        })
+    }
+}
+
+// SAFETY: Padding is explicit and will not contain uninitialized data.
+unsafe impl AsBytes for PackedRegistryEntry {}
+
+#[repr(transparent)]
+pub(crate) struct PackedRegistryTable {
+    inner: bindings::PACKED_REGISTRY_TABLE,
+}
+
+impl PackedRegistryTable {
+    #[allow(non_snake_case)]
+    pub(crate) fn init(num_entries: u32, size: u32) -> impl Init<Self> {
+        type InnerPackedRegistryTable = bindings::PACKED_REGISTRY_TABLE;
+        let init_inner = init!(InnerPackedRegistryTable {
+            numEntries: num_entries,
+            size,
+            entries: Default::default()
+        });
+
+        init!(PackedRegistryTable { inner <- init_inner })
+    }
+}
+
+// SAFETY: Padding is explicit and will not contain uninitialized data.
+unsafe impl AsBytes for PackedRegistryTable {}
+
+// SAFETY: This struct only contains integer types for which all bit patterns
+// are valid.
+unsafe impl FromBytes for PackedRegistryTable {}
diff --git a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs b/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs
index 1251b0c313ce..32933874ff97 100644
--- a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs
+++ b/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs
@@ -649,6 +649,22 @@ pub struct LibosMemoryRegionInitArgument {
     pub __bindgen_padding_0: [u8; 6usize],
 }
 #[repr(C)]
+#[derive(Debug, Default, Copy, Clone)]
+pub struct PACKED_REGISTRY_ENTRY {
+    pub nameOffset: u32_,
+    pub type_: u8_,
+    pub __bindgen_padding_0: [u8; 3usize],
+    pub data: u32_,
+    pub length: u32_,
+}
+#[repr(C)]
+#[derive(Debug, Default)]
+pub struct PACKED_REGISTRY_TABLE {
+    pub size: u32_,
+    pub numEntries: u32_,
+    pub entries: __IncompleteArrayField<PACKED_REGISTRY_ENTRY>,
+}
+#[repr(C)]
 #[derive(Debug, Default, Copy, Clone, Zeroable)]
 pub struct msgqTxHeader {
     pub version: u32_,
-- 
2.50.1


  parent reply	other threads:[~2025-10-13  6:21 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-13  6:20 [PATCH v5 00/14] gpu: nova-core: Boot GSP to RISC-V active Alistair Popple
2025-10-13  6:20 ` [PATCH v5 01/14] gpu: nova-core: Set correct DMA mask Alistair Popple
2025-10-13  6:20 ` [PATCH v5 02/14] gpu: nova-core: Create initial Gsp Alistair Popple
2025-10-16  6:22   ` Alexandre Courbot
2025-10-17  5:14     ` Alistair Popple
2025-10-13  6:20 ` [PATCH v5 03/14] gpu: nova-core: gsp: Create wpr metadata Alistair Popple
2025-10-16  6:23   ` Alexandre Courbot
2025-10-16 23:03     ` Alistair Popple
2025-10-16 23:11       ` Danilo Krummrich
2025-10-16 23:25         ` Miguel Ojeda
2025-10-17  0:43         ` Alexandre Courbot
2025-10-17  1:15           ` Alistair Popple
2025-10-17  1:38             ` Alexandre Courbot
2025-10-17 10:39               ` Danilo Krummrich
2025-10-20  5:40         ` Alexandre Courbot
2025-10-20 10:13           ` Danilo Krummrich
2025-10-20 10:50             ` Alexandre Courbot
2025-10-20 10:55               ` Danilo Krummrich
2025-10-13  6:20 ` [PATCH v5 04/14] gpu: nova-core: Add a slice-buffer (sbuffer) datastructure Alistair Popple
2025-10-16  6:23   ` Alexandre Courbot
2025-10-16 19:18     ` Miguel Ojeda
2025-10-17  4:45       ` Alistair Popple
2025-10-17  7:38         ` Alexandre Courbot
2025-10-13  6:20 ` [PATCH v5 05/14] gpu: nova-core: Add zeroable trait to bindings Alistair Popple
2025-10-13  6:20 ` [PATCH v5 06/14] gpu: nova-core: Add GSP command queue bindings Alistair Popple
2025-10-16  6:23   ` Alexandre Courbot
2025-10-16 19:22     ` Miguel Ojeda
2025-10-17  4:03       ` Alistair Popple
2025-10-13  6:20 ` [PATCH v5 07/14] gpu: nova-core: gsp: Add GSP command queue handling Alistair Popple
2025-10-16  6:24   ` Alexandre Courbot
2025-10-17  0:36     ` Alistair Popple
2025-10-16 18:44   ` Miguel Ojeda
2025-10-17  0:39     ` Alistair Popple
2025-10-13  6:20 ` [PATCH v5 08/14] gpu: nova-core: gsp: Create rmargs Alistair Popple
2025-10-16  6:24   ` Alexandre Courbot
2025-10-17  0:49     ` Alistair Popple
2025-10-13  6:20 ` [PATCH v5 09/14] gpu: nova-core: Add bindings and accessors for GspSystemInfo Alistair Popple
2025-10-16  6:24   ` Alexandre Courbot
2025-10-17  0:56     ` Alistair Popple
2025-10-17  1:41       ` Alexandre Courbot
2025-10-17  4:05         ` Alistair Popple
2025-10-13  6:20 ` Alistair Popple [this message]
2025-10-13  6:20 ` [PATCH v5 11/14] gpu: nova-core: gsp: Create RM registry and sysinfo commands Alistair Popple
2025-10-13  6:20 ` [PATCH v5 12/14] nova-core: falcon: Add support to check if RISC-V is active Alistair Popple
2025-10-13  6:20 ` [PATCH v5 13/14] nova-core: falcon: Add support to write firmware version Alistair Popple
2025-10-13  6:20 ` [PATCH v5 14/14] nova-core: gsp: Boot GSP Alistair Popple

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