From: Alistair Popple <apopple@nvidia.com>
To: rust-for-linux@vger.kernel.org, dri-devel@lists.freedesktop.org,
dakr@kernel.org, acourbot@nvidia.com
Cc: "Alistair Popple" <apopple@nvidia.com>,
"Miguel Ojeda" <ojeda@kernel.org>,
"Alex Gaynor" <alex.gaynor@gmail.com>,
"Boqun Feng" <boqun.feng@gmail.com>,
"Gary Guo" <gary@garyguo.net>,
"Björn Roy Baron" <bjorn3_gh@protonmail.com>,
"Benno Lossin" <lossin@kernel.org>,
"Andreas Hindborg" <a.hindborg@kernel.org>,
"Alice Ryhl" <aliceryhl@google.com>,
"Trevor Gross" <tmgross@umich.edu>,
"David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>,
"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Maxime Ripard" <mripard@kernel.org>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"John Hubbard" <jhubbard@nvidia.com>,
"Joel Fernandes" <joelagnelf@nvidia.com>,
"Timur Tabi" <ttabi@nvidia.com>,
linux-kernel@vger.kernel.org, nouveau@lists.freedesktop.org,
"Lyude Paul" <lyude@redhat.com>
Subject: [PATCH v5 12/14] nova-core: falcon: Add support to check if RISC-V is active
Date: Mon, 13 Oct 2025 17:20:38 +1100 [thread overview]
Message-ID: <20251013062041.1639529-13-apopple@nvidia.com> (raw)
In-Reply-To: <20251013062041.1639529-1-apopple@nvidia.com>
From: Joel Fernandes <joelagnelf@nvidia.com>
Add definition for RISCV_CPUCTL register and use it in a new falcon API
to check if the RISC-V core of a Falcon is active. It is required by
the sequencer to know if the GSP's RISCV processor is active.
Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
---
Changes for v4:
- Return bool instead of Result<bool> from is_riscv_active() as it
can't fail (thanks Timur).
- Update register definitions to correct Falcon
- Switch register definition order
---
drivers/gpu/nova-core/falcon.rs | 9 +++++++++
drivers/gpu/nova-core/regs.rs | 7 ++++++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs
index 734ac0fbfb49..185ed6d1cfb8 100644
--- a/drivers/gpu/nova-core/falcon.rs
+++ b/drivers/gpu/nova-core/falcon.rs
@@ -506,4 +506,13 @@ pub(crate) fn signature_reg_fuse_version(
self.hal
.signature_reg_fuse_version(self, bar, engine_id_mask, ucode_id)
}
+
+ /// Check if the RISC-V core is active.
+ ///
+ /// Returns `true` if the RISC-V core is active, `false` otherwise.
+ #[expect(unused)]
+ pub(crate) fn is_riscv_active(&self, bar: &Bar0) -> bool {
+ let cpuctl = regs::NV_PRISCV_RISCV_CPUCTL::read(bar, &E::ID);
+ cpuctl.active_stat()
+ }
}
diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs
index 0585699ae951..3bd1bddb16bb 100644
--- a/drivers/gpu/nova-core/regs.rs
+++ b/drivers/gpu/nova-core/regs.rs
@@ -324,7 +324,12 @@ pub(crate) fn mem_scrubbing_done(self) -> bool {
// PRISCV
-register!(NV_PRISCV_RISCV_BCR_CTRL @ PFalconBase[0x00001668] {
+register!(NV_PRISCV_RISCV_CPUCTL @ PFalcon2Base[0x00000388] {
+ 0:0 halted as bool;
+ 7:7 active_stat as bool;
+});
+
+register!(NV_PRISCV_RISCV_BCR_CTRL @ PFalcon2Base[0x00000668] {
0:0 valid as bool;
4:4 core_select as bool => PeregrineCoreSelect;
8:8 br_fetch as bool;
--
2.50.1
next prev parent reply other threads:[~2025-10-13 6:21 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-13 6:20 [PATCH v5 00/14] gpu: nova-core: Boot GSP to RISC-V active Alistair Popple
2025-10-13 6:20 ` [PATCH v5 01/14] gpu: nova-core: Set correct DMA mask Alistair Popple
2025-10-13 6:20 ` [PATCH v5 02/14] gpu: nova-core: Create initial Gsp Alistair Popple
2025-10-16 6:22 ` Alexandre Courbot
2025-10-17 5:14 ` Alistair Popple
2025-10-13 6:20 ` [PATCH v5 03/14] gpu: nova-core: gsp: Create wpr metadata Alistair Popple
2025-10-16 6:23 ` Alexandre Courbot
2025-10-16 23:03 ` Alistair Popple
2025-10-16 23:11 ` Danilo Krummrich
2025-10-16 23:25 ` Miguel Ojeda
2025-10-17 0:43 ` Alexandre Courbot
2025-10-17 1:15 ` Alistair Popple
2025-10-17 1:38 ` Alexandre Courbot
2025-10-17 10:39 ` Danilo Krummrich
2025-10-20 5:40 ` Alexandre Courbot
2025-10-20 10:13 ` Danilo Krummrich
2025-10-20 10:50 ` Alexandre Courbot
2025-10-20 10:55 ` Danilo Krummrich
2025-10-13 6:20 ` [PATCH v5 04/14] gpu: nova-core: Add a slice-buffer (sbuffer) datastructure Alistair Popple
2025-10-16 6:23 ` Alexandre Courbot
2025-10-16 19:18 ` Miguel Ojeda
2025-10-17 4:45 ` Alistair Popple
2025-10-17 7:38 ` Alexandre Courbot
2025-10-13 6:20 ` [PATCH v5 05/14] gpu: nova-core: Add zeroable trait to bindings Alistair Popple
2025-10-13 6:20 ` [PATCH v5 06/14] gpu: nova-core: Add GSP command queue bindings Alistair Popple
2025-10-16 6:23 ` Alexandre Courbot
2025-10-16 19:22 ` Miguel Ojeda
2025-10-17 4:03 ` Alistair Popple
2025-10-13 6:20 ` [PATCH v5 07/14] gpu: nova-core: gsp: Add GSP command queue handling Alistair Popple
2025-10-16 6:24 ` Alexandre Courbot
2025-10-17 0:36 ` Alistair Popple
2025-10-16 18:44 ` Miguel Ojeda
2025-10-17 0:39 ` Alistair Popple
2025-10-13 6:20 ` [PATCH v5 08/14] gpu: nova-core: gsp: Create rmargs Alistair Popple
2025-10-16 6:24 ` Alexandre Courbot
2025-10-17 0:49 ` Alistair Popple
2025-10-13 6:20 ` [PATCH v5 09/14] gpu: nova-core: Add bindings and accessors for GspSystemInfo Alistair Popple
2025-10-16 6:24 ` Alexandre Courbot
2025-10-17 0:56 ` Alistair Popple
2025-10-17 1:41 ` Alexandre Courbot
2025-10-17 4:05 ` Alistair Popple
2025-10-13 6:20 ` [PATCH v5 10/14] gpu: nova-core: Add bindings for the GSP RM registry tables Alistair Popple
2025-10-13 6:20 ` [PATCH v5 11/14] gpu: nova-core: gsp: Create RM registry and sysinfo commands Alistair Popple
2025-10-13 6:20 ` Alistair Popple [this message]
2025-10-13 6:20 ` [PATCH v5 13/14] nova-core: falcon: Add support to write firmware version Alistair Popple
2025-10-13 6:20 ` [PATCH v5 14/14] nova-core: gsp: Boot GSP Alistair Popple
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20251013062041.1639529-13-apopple@nvidia.com \
--to=apopple@nvidia.com \
--cc=a.hindborg@kernel.org \
--cc=acourbot@nvidia.com \
--cc=airlied@gmail.com \
--cc=alex.gaynor@gmail.com \
--cc=aliceryhl@google.com \
--cc=bjorn3_gh@protonmail.com \
--cc=boqun.feng@gmail.com \
--cc=dakr@kernel.org \
--cc=dri-devel@lists.freedesktop.org \
--cc=gary@garyguo.net \
--cc=jhubbard@nvidia.com \
--cc=joelagnelf@nvidia.com \
--cc=linux-kernel@vger.kernel.org \
--cc=lossin@kernel.org \
--cc=lyude@redhat.com \
--cc=maarten.lankhorst@linux.intel.com \
--cc=mripard@kernel.org \
--cc=nouveau@lists.freedesktop.org \
--cc=ojeda@kernel.org \
--cc=rust-for-linux@vger.kernel.org \
--cc=simona@ffwll.ch \
--cc=tmgross@umich.edu \
--cc=ttabi@nvidia.com \
--cc=tzimmermann@suse.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®