From: James Morse <james.morse@arm.com>
To: linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org
Cc: James Morse <james.morse@arm.com>,
D Scott Phillips OS <scott@os.amperecomputing.com>,
carl@os.amperecomputing.com, lcherian@marvell.com,
bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com,
baolin.wang@linux.alibaba.com,
Jamie Iles <quic_jiles@quicinc.com>,
Xin Hao <xhao@linux.alibaba.com>,
peternewman@google.com, dfustini@baylibre.com,
amitsinght@marvell.com, David Hildenbrand <david@redhat.com>,
Dave Martin <dave.martin@arm.com>, Koba Ko <kobak@nvidia.com>,
Shanker Donthineni <sdonthineni@nvidia.com>,
fenghuay@nvidia.com, baisheng.gao@unisoc.com,
Jonathan Cameron <jonathan.cameron@huawei.com>,
Rob Herring <robh@kernel.org>,
Rohit Mathew <rohit.mathew@arm.com>,
Rafael Wysocki <rafael@kernel.org>, Len Brown <lenb@kernel.org>,
Lorenzo Pieralisi <lpieralisi@kernel.org>,
Hanjun Guo <guohanjun@huawei.com>,
Sudeep Holla <sudeep.holla@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Danilo Krummrich <dakr@kernel.org>,
Jeremy Linton <jeremy.linton@arm.com>,
Gavin Shan <gshan@redhat.com>, Ben Horgan <ben.horgan@arm.com>
Subject: [PATCH v3 08/29] arm_mpam: Add the class and component structures for firmware described ris
Date: Fri, 17 Oct 2025 18:56:24 +0000 [thread overview]
Message-ID: <20251017185645.26604-9-james.morse@arm.com> (raw)
In-Reply-To: <20251017185645.26604-1-james.morse@arm.com>
An MSC is a container of resources, each identified by their RIS index.
Some RIS are described by firmware to provide their position in the system.
Others are discovered when the driver probes the hardware.
To configure a resource it needs to be found by its class, e.g. 'L2'.
There are two kinds of grouping, a class is a set of components, which
are visible to user-space as there are likely to be multiple instances
of the L2 cache. (e.g. one per cluster or package)
Add support for creating and destroying structures to allow a hierarchy
of resources to be created.
CC: Ben Horgan <ben.horgan@arm.com>
Tested-by: Fenghua Yu <fenghuay@nvidia.com>
Signed-off-by: James Morse <james.morse@arm.com>
---
Changes since v2:
* Renamed _get functions _find to avoid folk looking for _put.
* Made init_garbage a static-inline.
* Moved garbage pdev assignment closer to allocation to make that pattern
clearer.
* Return found MSC when 'finding' as there is no longer a lock to unlock.
* Added initialisation of ris->msc_list.
* Use dev_warn_once() in preference to printing the device name.
Changes since v1:
* Fixed a comp/vmsc typo.
* Removed duplicate description from the commit message.
* Moved parenthesis in the add_to_garbage() macro.
* Check for out of range ris_idx when creating ris.
* Removed GFP as probe_lock is no longer a spin lock.
* Removed alloc flag as ended up searching the lists itself.
* Added a comment about affinity masks not overlapping.
Changes since RFC:
* removed a pr_err() debug message that crept in.
---
drivers/resctrl/mpam_devices.c | 390 +++++++++++++++++++++++++++++++-
drivers/resctrl/mpam_internal.h | 93 ++++++++
include/linux/arm_mpam.h | 8 +-
3 files changed, 483 insertions(+), 8 deletions(-)
diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c
index d18eeec95f79..8685e50f08c6 100644
--- a/drivers/resctrl/mpam_devices.c
+++ b/drivers/resctrl/mpam_devices.c
@@ -30,7 +30,7 @@
static DEFINE_MUTEX(mpam_list_lock);
static LIST_HEAD(mpam_all_msc);
-static struct srcu_struct mpam_srcu;
+struct srcu_struct mpam_srcu;
/*
* Number of MSCs that have been probed. Once all MSC have been probed MPAM
@@ -38,6 +38,379 @@ static struct srcu_struct mpam_srcu;
*/
static atomic_t mpam_num_msc;
+/*
+ * An MSC is a physical container for controls and monitors, each identified by
+ * their RIS index. These share a base-address, interrupts and some MMIO
+ * registers. A vMSC is a virtual container for RIS in an MSC that control or
+ * monitor the same thing. Members of a vMSC are all RIS in the same MSC, but
+ * not all RIS in an MSC share a vMSC.
+ * Components are a group of vMSC that control or monitor the same thing but
+ * are from different MSC, so have different base-address, interrupts etc.
+ * Classes are the set components of the same type.
+ *
+ * The features of a vMSC is the union of the RIS it contains.
+ * The features of a Class and Component are the common subset of the vMSC
+ * they contain.
+ *
+ * e.g. The system cache may have bandwidth controls on multiple interfaces,
+ * for regulating traffic from devices independently of traffic from CPUs.
+ * If these are two RIS in one MSC, they will be treated as controlling
+ * different things, and will not share a vMSC/component/class.
+ *
+ * e.g. The L2 may have one MSC and two RIS, one for cache-controls another
+ * for bandwidth. These two RIS are members of the same vMSC.
+ *
+ * e.g. The set of RIS that make up the L2 are grouped as a component. These
+ * are sometimes termed slices. They should be configured the same, as if there
+ * were only one.
+ *
+ * e.g. The SoC probably has more than one L2, each attached to a distinct set
+ * of CPUs. All the L2 components are grouped as a class.
+ *
+ * When creating an MSC, struct mpam_msc is added to the all mpam_all_msc list,
+ * then linked via struct mpam_ris to a vmsc, component and class.
+ * The same MSC may exist under different class->component->vmsc paths, but the
+ * RIS index will be unique.
+ */
+LIST_HEAD(mpam_classes);
+
+/* List of all objects that can be free()d after synchronise_srcu() */
+static LLIST_HEAD(mpam_garbage);
+
+static inline void init_garbage(struct mpam_garbage *garbage)
+{
+ init_llist_node(&garbage->llist);
+}
+
+static struct mpam_vmsc *
+mpam_vmsc_alloc(struct mpam_component *comp, struct mpam_msc *msc)
+{
+ struct mpam_vmsc *vmsc;
+
+ lockdep_assert_held(&mpam_list_lock);
+
+ vmsc = kzalloc(sizeof(*vmsc), GFP_KERNEL);
+ if (!vmsc)
+ return ERR_PTR(-ENOMEM);
+ init_garbage(&vmsc->garbage);
+
+ INIT_LIST_HEAD_RCU(&vmsc->ris);
+ INIT_LIST_HEAD_RCU(&vmsc->comp_list);
+ vmsc->comp = comp;
+ vmsc->msc = msc;
+
+ list_add_rcu(&vmsc->comp_list, &comp->vmsc);
+
+ return vmsc;
+}
+
+static struct mpam_vmsc *mpam_vmsc_find(struct mpam_component *comp,
+ struct mpam_msc *msc)
+{
+ struct mpam_vmsc *vmsc;
+
+ lockdep_assert_held(&mpam_list_lock);
+
+ list_for_each_entry(vmsc, &comp->vmsc, comp_list) {
+ if (vmsc->msc->id == msc->id)
+ return vmsc;
+ }
+
+ return mpam_vmsc_alloc(comp, msc);
+}
+
+static struct mpam_component *
+mpam_component_alloc(struct mpam_class *class, int id)
+{
+ struct mpam_component *comp;
+
+ lockdep_assert_held(&mpam_list_lock);
+
+ comp = kzalloc(sizeof(*comp), GFP_KERNEL);
+ if (!comp)
+ return ERR_PTR(-ENOMEM);
+ init_garbage(&comp->garbage);
+
+ comp->comp_id = id;
+ INIT_LIST_HEAD_RCU(&comp->vmsc);
+ /* affinity is updated when ris are added */
+ INIT_LIST_HEAD_RCU(&comp->class_list);
+ comp->class = class;
+
+ list_add_rcu(&comp->class_list, &class->components);
+
+ return comp;
+}
+
+static struct mpam_component *
+mpam_component_find(struct mpam_class *class, int id)
+{
+ struct mpam_component *comp;
+
+ lockdep_assert_held(&mpam_list_lock);
+
+ list_for_each_entry(comp, &class->components, class_list) {
+ if (comp->comp_id == id)
+ return comp;
+ }
+
+ return mpam_component_alloc(class, id);
+}
+
+static struct mpam_class *
+mpam_class_alloc(u8 level_idx, enum mpam_class_types type)
+{
+ struct mpam_class *class;
+
+ lockdep_assert_held(&mpam_list_lock);
+
+ class = kzalloc(sizeof(*class), GFP_KERNEL);
+ if (!class)
+ return ERR_PTR(-ENOMEM);
+ init_garbage(&class->garbage);
+
+ INIT_LIST_HEAD_RCU(&class->components);
+ /* affinity is updated when ris are added */
+ class->level = level_idx;
+ class->type = type;
+ INIT_LIST_HEAD_RCU(&class->classes_list);
+
+ list_add_rcu(&class->classes_list, &mpam_classes);
+
+ return class;
+}
+
+static struct mpam_class *
+mpam_class_find(u8 level_idx, enum mpam_class_types type)
+{
+ struct mpam_class *class;
+
+ lockdep_assert_held(&mpam_list_lock);
+
+ list_for_each_entry(class, &mpam_classes, classes_list) {
+ if (class->type == type && class->level == level_idx)
+ return class;
+ }
+
+ return mpam_class_alloc(level_idx, type);
+}
+
+#define add_to_garbage(x) \
+do { \
+ __typeof__(x) _x = (x); \
+ _x->garbage.to_free = _x; \
+ llist_add(&_x->garbage.llist, &mpam_garbage); \
+} while (0)
+
+static void mpam_class_destroy(struct mpam_class *class)
+{
+ lockdep_assert_held(&mpam_list_lock);
+
+ list_del_rcu(&class->classes_list);
+ add_to_garbage(class);
+}
+
+static void mpam_comp_destroy(struct mpam_component *comp)
+{
+ struct mpam_class *class = comp->class;
+
+ lockdep_assert_held(&mpam_list_lock);
+
+ list_del_rcu(&comp->class_list);
+ add_to_garbage(comp);
+
+ if (list_empty(&class->components))
+ mpam_class_destroy(class);
+}
+
+static void mpam_vmsc_destroy(struct mpam_vmsc *vmsc)
+{
+ struct mpam_component *comp = vmsc->comp;
+
+ lockdep_assert_held(&mpam_list_lock);
+
+ list_del_rcu(&vmsc->comp_list);
+ add_to_garbage(vmsc);
+
+ if (list_empty(&comp->vmsc))
+ mpam_comp_destroy(comp);
+}
+
+static void mpam_ris_destroy(struct mpam_msc_ris *ris)
+{
+ struct mpam_vmsc *vmsc = ris->vmsc;
+ struct mpam_msc *msc = vmsc->msc;
+ struct mpam_component *comp = vmsc->comp;
+ struct mpam_class *class = comp->class;
+
+ lockdep_assert_held(&mpam_list_lock);
+
+ /*
+ * It is assumed affinities don't overlap. If they do the class becomes
+ * unusable immediately.
+ */
+ cpumask_andnot(&comp->affinity, &comp->affinity, &ris->affinity);
+ cpumask_andnot(&class->affinity, &class->affinity, &ris->affinity);
+ clear_bit(ris->ris_idx, &msc->ris_idxs);
+ list_del_rcu(&ris->vmsc_list);
+ list_del_rcu(&ris->msc_list);
+ add_to_garbage(ris);
+
+ if (list_empty(&vmsc->ris))
+ mpam_vmsc_destroy(vmsc);
+}
+
+static void mpam_free_garbage(void)
+{
+ struct mpam_garbage *iter, *tmp;
+ struct llist_node *to_free = llist_del_all(&mpam_garbage);
+
+ if (!to_free)
+ return;
+
+ synchronize_srcu(&mpam_srcu);
+
+ llist_for_each_entry_safe(iter, tmp, to_free, llist) {
+ if (iter->pdev)
+ devm_kfree(&iter->pdev->dev, iter->to_free);
+ else
+ kfree(iter->to_free);
+ }
+}
+
+/*
+ * The cacheinfo structures are only populated when CPUs are online.
+ * This helper walks the device tree to include offline CPUs too.
+ */
+int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level,
+ cpumask_t *affinity)
+{
+ return acpi_pptt_get_cpumask_from_cache_id(cache_id, affinity);
+}
+
+/*
+ * cpumask_of_node() only knows about online CPUs. This can't tell us whether
+ * a class is represented on all possible CPUs.
+ */
+static void get_cpumask_from_node_id(u32 node_id, cpumask_t *affinity)
+{
+ int cpu;
+
+ for_each_possible_cpu(cpu) {
+ if (node_id == cpu_to_node(cpu))
+ cpumask_set_cpu(cpu, affinity);
+ }
+}
+
+static int mpam_ris_get_affinity(struct mpam_msc *msc, cpumask_t *affinity,
+ enum mpam_class_types type,
+ struct mpam_class *class,
+ struct mpam_component *comp)
+{
+ int err;
+
+ switch (type) {
+ case MPAM_CLASS_CACHE:
+ err = mpam_get_cpumask_from_cache_id(comp->comp_id, class->level,
+ affinity);
+ if (err)
+ return err;
+
+ if (cpumask_empty(affinity))
+ dev_warn_once(&msc->pdev->dev,
+ "no CPUs associated with cache node\n");
+
+ break;
+ case MPAM_CLASS_MEMORY:
+ get_cpumask_from_node_id(comp->comp_id, affinity);
+ /* affinity may be empty for CPU-less memory nodes */
+ break;
+ case MPAM_CLASS_UNKNOWN:
+ return 0;
+ }
+
+ cpumask_and(affinity, affinity, &msc->accessibility);
+
+ return 0;
+}
+
+static int mpam_ris_create_locked(struct mpam_msc *msc, u8 ris_idx,
+ enum mpam_class_types type, u8 class_id,
+ int component_id)
+{
+ int err;
+ struct mpam_vmsc *vmsc;
+ struct mpam_msc_ris *ris;
+ struct mpam_class *class;
+ struct mpam_component *comp;
+ struct platform_device *pdev = msc->pdev;
+
+ lockdep_assert_held(&mpam_list_lock);
+
+ if (ris_idx > MPAM_MSC_MAX_NUM_RIS)
+ return -EINVAL;
+
+ if (test_and_set_bit(ris_idx, &msc->ris_idxs))
+ return -EBUSY;
+
+ ris = devm_kzalloc(&msc->pdev->dev, sizeof(*ris), GFP_KERNEL);
+ if (!ris)
+ return -ENOMEM;
+ init_garbage(&ris->garbage);
+ ris->garbage.pdev = pdev;
+
+ class = mpam_class_find(class_id, type);
+ if (IS_ERR(class))
+ return PTR_ERR(class);
+
+ comp = mpam_component_find(class, component_id);
+ if (IS_ERR(comp)) {
+ if (list_empty(&class->components))
+ mpam_class_destroy(class);
+ return PTR_ERR(comp);
+ }
+
+ vmsc = mpam_vmsc_find(comp, msc);
+ if (IS_ERR(vmsc)) {
+ if (list_empty(&comp->vmsc))
+ mpam_comp_destroy(comp);
+ return PTR_ERR(vmsc);
+ }
+
+ err = mpam_ris_get_affinity(msc, &ris->affinity, type, class, comp);
+ if (err) {
+ if (list_empty(&vmsc->ris))
+ mpam_vmsc_destroy(vmsc);
+ return err;
+ }
+
+ ris->ris_idx = ris_idx;
+ INIT_LIST_HEAD_RCU(&ris->msc_list);
+ INIT_LIST_HEAD_RCU(&ris->vmsc_list);
+ ris->vmsc = vmsc;
+
+ cpumask_or(&comp->affinity, &comp->affinity, &ris->affinity);
+ cpumask_or(&class->affinity, &class->affinity, &ris->affinity);
+ list_add_rcu(&ris->vmsc_list, &vmsc->ris);
+
+ return 0;
+}
+
+int mpam_ris_create(struct mpam_msc *msc, u8 ris_idx,
+ enum mpam_class_types type, u8 class_id, int component_id)
+{
+ int err;
+
+ mutex_lock(&mpam_list_lock);
+ err = mpam_ris_create_locked(msc, ris_idx, type, class_id,
+ component_id);
+ mutex_unlock(&mpam_list_lock);
+ if (err)
+ mpam_free_garbage();
+
+ return err;
+}
+
/*
* An MSC can control traffic from a set of CPUs, but may only be accessible
* from a (hopefully wider) set of CPUs. The common reason for this is power
@@ -62,14 +435,25 @@ static int update_msc_accessibility(struct mpam_msc *msc)
static int fw_num_msc;
+/*
+ * There are two ways of reaching a struct mpam_msc_ris. Via the
+ * class->component->vmsc->ris, or via the msc.
+ * When destroying the msc, the other side needs unlinking and cleaning up too.
+ */
static void mpam_msc_destroy(struct mpam_msc *msc)
{
struct platform_device *pdev = msc->pdev;
+ struct mpam_msc_ris *ris, *tmp;
lockdep_assert_held(&mpam_list_lock);
+ list_for_each_entry_safe(ris, tmp, &msc->ris, msc_list)
+ mpam_ris_destroy(ris);
+
list_del_rcu(&msc->all_msc_list);
platform_set_drvdata(pdev, NULL);
+
+ add_to_garbage(msc);
}
static void mpam_msc_drv_remove(struct platform_device *pdev)
@@ -83,7 +467,7 @@ static void mpam_msc_drv_remove(struct platform_device *pdev)
mpam_msc_destroy(msc);
mutex_unlock(&mpam_list_lock);
- synchronize_srcu(&mpam_srcu);
+ mpam_free_garbage();
}
static struct mpam_msc *do_mpam_msc_drv_probe(struct platform_device *pdev)
@@ -99,6 +483,8 @@ static struct mpam_msc *do_mpam_msc_drv_probe(struct platform_device *pdev)
msc = devm_kzalloc(&pdev->dev, sizeof(*msc), GFP_KERNEL);
if (!msc)
return ERR_PTR(-ENOMEM);
+ init_garbage(&msc->garbage);
+ msc->garbage.pdev = pdev;
mutex_init(&msc->probe_lock);
mutex_init(&msc->part_sel_lock);
diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_internal.h
index 6ac75f3613c3..1a5d96660382 100644
--- a/drivers/resctrl/mpam_internal.h
+++ b/drivers/resctrl/mpam_internal.h
@@ -7,14 +7,32 @@
#include <linux/arm_mpam.h>
#include <linux/cpumask.h>
#include <linux/io.h>
+#include <linux/llist.h>
#include <linux/mailbox_client.h>
#include <linux/mutex.h>
#include <linux/sizes.h>
#include <linux/spinlock.h>
#include <linux/srcu.h>
+#define MPAM_MSC_MAX_NUM_RIS 16
+
struct platform_device;
+/*
+ * Structures protected by SRCU may not be freed for a surprising amount of
+ * time (especially if perf is running). To ensure the MPAM error interrupt can
+ * tear down all the structures, build a list of objects that can be gargbage
+ * collected once synchronize_srcu() has returned.
+ * If pdev is non-NULL, use devm_kfree().
+ */
+struct mpam_garbage {
+ /* member of mpam_garbage */
+ struct llist_node llist;
+
+ void *to_free;
+ struct platform_device *pdev;
+};
+
struct mpam_msc {
/* member of mpam_all_msc */
struct list_head all_msc_list;
@@ -48,5 +66,80 @@ struct mpam_msc {
void __iomem *mapped_hwpage;
size_t mapped_hwpage_sz;
+
+ struct mpam_garbage garbage;
};
+
+struct mpam_class {
+ /* mpam_components in this class */
+ struct list_head components;
+
+ cpumask_t affinity;
+
+ u8 level;
+ enum mpam_class_types type;
+
+ /* member of mpam_classes */
+ struct list_head classes_list;
+
+ struct mpam_garbage garbage;
+};
+
+struct mpam_component {
+ u32 comp_id;
+
+ /* mpam_vmsc in this component */
+ struct list_head vmsc;
+
+ cpumask_t affinity;
+
+ /* member of mpam_class:components */
+ struct list_head class_list;
+
+ /* parent: */
+ struct mpam_class *class;
+
+ struct mpam_garbage garbage;
+};
+
+struct mpam_vmsc {
+ /* member of mpam_component:vmsc_list */
+ struct list_head comp_list;
+
+ /* mpam_msc_ris in this vmsc */
+ struct list_head ris;
+
+ /* All RIS in this vMSC are members of this MSC */
+ struct mpam_msc *msc;
+
+ /* parent: */
+ struct mpam_component *comp;
+
+ struct mpam_garbage garbage;
+};
+
+struct mpam_msc_ris {
+ u8 ris_idx;
+
+ cpumask_t affinity;
+
+ /* member of mpam_vmsc:ris */
+ struct list_head vmsc_list;
+
+ /* member of mpam_msc:ris */
+ struct list_head msc_list;
+
+ /* parent: */
+ struct mpam_vmsc *vmsc;
+
+ struct mpam_garbage garbage;
+};
+
+/* List of all classes - protected by srcu*/
+extern struct srcu_struct mpam_srcu;
+extern struct list_head mpam_classes;
+
+int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level,
+ cpumask_t *affinity);
+
#endif /* MPAM_INTERNAL_H */
diff --git a/include/linux/arm_mpam.h b/include/linux/arm_mpam.h
index 3d6c39c667c3..3206f5ddc147 100644
--- a/include/linux/arm_mpam.h
+++ b/include/linux/arm_mpam.h
@@ -38,11 +38,7 @@ static inline int acpi_mpam_parse_resources(struct mpam_msc *msc,
static inline int acpi_mpam_count_msc(void) { return -EINVAL; }
#endif
-static inline int mpam_ris_create(struct mpam_msc *msc, u8 ris_idx,
- enum mpam_class_types type, u8 class_id,
- int component_id)
-{
- return -EINVAL;
-}
+int mpam_ris_create(struct mpam_msc *msc, u8 ris_idx,
+ enum mpam_class_types type, u8 class_id, int component_id);
#endif /* __LINUX_ARM_MPAM_H */
--
2.39.5
next prev parent reply other threads:[~2025-10-17 18:57 UTC|newest]
Thread overview: 108+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-17 18:56 [PATCH v3 00/29] arm_mpam: Add basic mpam driver James Morse
2025-10-17 18:56 ` [PATCH v3 01/29] ACPI / PPTT: Add a helper to fill a cpumask from a processor container James Morse
2025-10-24 11:26 ` Jonathan Cameron
2025-11-06 16:09 ` Ben Horgan
2025-10-17 18:56 ` [PATCH v3 02/29] ACPI / PPTT: Stop acpi_count_levels() expecting callers to clear levels James Morse
2025-10-24 11:29 ` Jonathan Cameron
2025-11-06 16:10 ` Ben Horgan
2025-10-17 18:56 ` [PATCH v3 03/29] ACPI / PPTT: Find cache level by cache-id James Morse
2025-10-20 10:34 ` Ben Horgan
2025-10-24 14:15 ` Jonathan Cameron
2025-10-17 18:56 ` [PATCH v3 04/29] ACPI / PPTT: Add a helper to fill a cpumask from a cache_id James Morse
2025-10-20 10:45 ` Ben Horgan
2025-10-22 12:58 ` Jeremy Linton
2025-10-24 14:22 ` Jonathan Cameron
2025-11-06 16:18 ` Ben Horgan
2025-10-17 18:56 ` [PATCH v3 05/29] arm64: kconfig: Add Kconfig entry for MPAM James Morse
2025-10-17 18:56 ` [PATCH v3 06/29] ACPI / MPAM: Parse the MPAM table James Morse
2025-10-20 12:29 ` Ben Horgan
2025-10-24 16:13 ` Jonathan Cameron
2025-11-06 16:55 ` Ben Horgan
2025-10-17 18:56 ` [PATCH v3 07/29] arm_mpam: Add probe/remove for mpam msc driver and kbuild boiler plate James Morse
2025-10-20 12:43 ` Ben Horgan
2025-10-20 15:44 ` Ben Horgan
2025-10-21 9:51 ` Ben Horgan
2025-10-22 0:29 ` Fenghua Yu
2025-10-22 19:00 ` Tushar Dave
2025-10-24 16:25 ` Jonathan Cameron
2025-11-06 17:48 ` Markus Elfring
2025-10-17 18:56 ` James Morse [this message]
2025-10-24 16:47 ` [PATCH v3 08/29] arm_mpam: Add the class and component structures for firmware described ris Jonathan Cameron
2025-11-06 17:43 ` Ben Horgan
2025-10-17 18:56 ` [PATCH v3 09/29] arm_mpam: Add MPAM MSC register layout definitions James Morse
2025-10-17 23:03 ` Fenghua Yu
2025-10-24 17:32 ` Jonathan Cameron
2025-10-27 16:33 ` Ben Horgan
2025-10-29 6:37 ` Shaopeng Tan (Fujitsu)
2025-10-17 18:56 ` [PATCH v3 10/29] arm_mpam: Add cpuhp callbacks to probe MSC hardware James Morse
2025-10-29 7:24 ` Shaopeng Tan (Fujitsu)
2025-10-17 18:56 ` [PATCH v3 11/29] arm_mpam: Probe hardware to find the supported partid/pmg values James Morse
2025-10-24 17:40 ` Jonathan Cameron
2025-10-17 18:56 ` [PATCH v3 12/29] arm_mpam: Add helpers for managing the locking around the mon_sel registers James Morse
2025-10-24 17:43 ` Jonathan Cameron
2025-10-17 18:56 ` [PATCH v3 13/29] arm_mpam: Probe the hardware features resctrl supports James Morse
2025-10-24 17:47 ` Jonathan Cameron
2025-10-17 18:56 ` [PATCH v3 14/29] arm_mpam: Merge supported features during mpam_enable() into mpam_class James Morse
2025-10-17 18:56 ` [PATCH v3 15/29] arm_mpam: Reset MSC controls from cpuhp callbacks James Morse
2025-10-24 17:52 ` Jonathan Cameron
2025-10-29 6:53 ` Shaopeng Tan (Fujitsu)
2025-10-17 18:56 ` [PATCH v3 16/29] arm_mpam: Add a helper to touch an MSC from any CPU James Morse
2025-10-17 18:56 ` [PATCH v3 17/29] arm_mpam: Extend reset logic to allow devices to be reset any time James Morse
2025-10-20 15:14 ` Ben Horgan
2025-10-17 18:56 ` [PATCH v3 18/29] arm_mpam: Register and enable IRQs James Morse
2025-10-24 18:03 ` Jonathan Cameron
2025-10-29 7:02 ` Shaopeng Tan (Fujitsu)
2025-10-17 18:56 ` [PATCH v3 19/29] arm_mpam: Use a static key to indicate when mpam is enabled James Morse
2025-10-20 16:28 ` Ben Horgan
2025-10-17 18:56 ` [PATCH v3 20/29] arm_mpam: Allow configuration to be applied and restored during cpu online James Morse
2025-10-20 17:04 ` Ben Horgan
2025-10-27 8:47 ` Shaopeng Tan (Fujitsu)
2025-11-05 16:16 ` Peter Newman
2025-11-06 10:11 ` Ben Horgan
2025-10-29 7:09 ` Shaopeng Tan (Fujitsu)
2025-10-17 18:56 ` [PATCH v3 21/29] arm_mpam: Probe and reset the rest of the features James Morse
2025-10-20 17:16 ` Ben Horgan
2025-10-17 18:56 ` [PATCH v3 22/29] arm_mpam: Add helpers to allocate monitors James Morse
2025-10-17 18:56 ` [PATCH v3 23/29] arm_mpam: Add mpam_msmon_read() to read monitor value James Morse
2025-10-24 18:18 ` Jonathan Cameron
2025-11-05 8:32 ` Shaopeng Tan (Fujitsu)
2025-11-05 12:11 ` Ben Horgan
2025-11-07 5:01 ` Shaopeng Tan (Fujitsu)
2025-11-07 10:01 ` Ben Horgan
2025-10-17 18:56 ` [PATCH v3 24/29] arm_mpam: Track bandwidth counter state for overflow and power management James Morse
2025-10-22 13:39 ` [PATCH mpam mpam/snapshot/v6.14-rc1] arm64/mpam: Fix MBWU monitor overflow handling Zeng Heng
2025-10-22 16:17 ` Ben Horgan
2025-10-25 8:45 ` Zeng Heng
2025-10-25 9:34 ` [PATCH] arm64/mpam: Clean MBWU monitor overflow bit Zeng Heng
2025-10-28 17:37 ` Ben Horgan
2025-10-28 17:04 ` [PATCH mpam mpam/snapshot/v6.14-rc1] arm64/mpam: Fix MBWU monitor overflow handling Ben Horgan
2025-10-25 9:01 ` Zeng Heng
2025-10-28 16:01 ` Ben Horgan
2025-10-29 2:49 ` Zeng Heng
2025-10-29 3:59 ` Zeng Heng
2025-10-24 18:22 ` [PATCH v3 24/29] arm_mpam: Track bandwidth counter state for overflow and power management Jonathan Cameron
2025-10-29 7:56 ` [PATCH v2] arm64/mpam: Clean MBWU monitor overflow bit Zeng Heng
2025-10-30 9:52 ` Ben Horgan
2025-11-03 3:47 ` Zeng Heng
2025-11-04 10:24 ` Ben Horgan
2025-11-04 13:48 ` Zeng Heng
2025-10-17 18:56 ` [PATCH v3 25/29] arm_mpam: Probe for long/lwd mbwu counters James Morse
2025-10-22 11:23 ` Ben Horgan
2025-10-24 18:24 ` Jonathan Cameron
2025-10-17 18:56 ` [PATCH v3 26/29] arm_mpam: Use long MBWU counters if supported James Morse
2025-10-22 12:31 ` Ben Horgan
2025-10-24 18:29 ` Jonathan Cameron
2025-11-06 15:18 ` Peter Newman
2025-11-06 15:43 ` Ben Horgan
2025-11-06 16:15 ` Peter Newman
2025-11-06 16:41 ` Ben Horgan
2025-11-07 10:30 ` Peter Newman
2025-11-07 10:53 ` Ben Horgan
2025-10-17 18:56 ` [PATCH v3 27/29] arm_mpam: Add helper to reset saved mbwu state James Morse
2025-10-24 18:34 ` Jonathan Cameron
2025-10-29 7:14 ` Shaopeng Tan (Fujitsu)
2025-10-17 18:56 ` [PATCH v3 28/29] arm_mpam: Add kunit test for bitmap reset James Morse
2025-10-17 18:56 ` [PATCH v3 29/29] arm_mpam: Add kunit tests for props_mismatch() James Morse
2025-10-18 1:01 ` [PATCH v3 00/29] arm_mpam: Add basic mpam driver Fenghua Yu
2025-10-23 8:15 ` Shaopeng Tan (Fujitsu)
2025-11-05 9:39 ` Peter Newman
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20251017185645.26604-9-james.morse@arm.com \
--to=james.morse@arm.com \
--cc=amitsinght@marvell.com \
--cc=baisheng.gao@unisoc.com \
--cc=baolin.wang@linux.alibaba.com \
--cc=ben.horgan@arm.com \
--cc=bobo.shaobowang@huawei.com \
--cc=carl@os.amperecomputing.com \
--cc=catalin.marinas@arm.com \
--cc=dakr@kernel.org \
--cc=dave.martin@arm.com \
--cc=david@redhat.com \
--cc=dfustini@baylibre.com \
--cc=fenghuay@nvidia.com \
--cc=gregkh@linuxfoundation.org \
--cc=gshan@redhat.com \
--cc=guohanjun@huawei.com \
--cc=jeremy.linton@arm.com \
--cc=jonathan.cameron@huawei.com \
--cc=kobak@nvidia.com \
--cc=lcherian@marvell.com \
--cc=lenb@kernel.org \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=lpieralisi@kernel.org \
--cc=peternewman@google.com \
--cc=quic_jiles@quicinc.com \
--cc=rafael@kernel.org \
--cc=robh@kernel.org \
--cc=rohit.mathew@arm.com \
--cc=scott@os.amperecomputing.com \
--cc=sdonthineni@nvidia.com \
--cc=sudeep.holla@arm.com \
--cc=tan.shaopeng@fujitsu.com \
--cc=will@kernel.org \
--cc=xhao@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
Powered by JetHome