[PATCH] arm64: dts: amlogic: meson-g12b: Fix L2 cache reference for S922X CPUs

[PATCH] arm64: dts: amlogic: meson-g12b: Fix L2 cache reference for S922X CPUs

[Guillaume La Roque]

The original addition of cache information for the Amlogic S922X SoC
used the wrong next-level cache node for CPU cores 100 and 101,
incorrectly referencing `l2_cache_l`. These cores actually belong to
the big cluster and should reference `l2_cache_b`. Update the device
tree accordingly.

Fixes: e7f85e6c155a ("arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC")
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
---
 arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
index f04efa828256..23358d94844c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
@@ -87,7 +87,7 @@ cpu100: cpu@100 {
 			i-cache-line-size = <32>;
 			i-cache-size = <0x8000>;
 			i-cache-sets = <32>;
-			next-level-cache = <&l2_cache_l>;
+			next-level-cache = <&l2_cache_b>;
 			#cooling-cells = <2>;
 		};
 
@@ -103,7 +103,7 @@ cpu101: cpu@101 {
 			i-cache-line-size = <32>;
 			i-cache-size = <0x8000>;
 			i-cache-sets = <32>;
-			next-level-cache = <&l2_cache_l>;
+			next-level-cache = <&l2_cache_b>;
 			#cooling-cells = <2>;
 		};
 

---
base-commit: 6a23ae0a96a600d1d12557add110e0bb6e32730c
change-id: 20251123-fixkhadas-c84da7d7c47c

Best regards,
-- 
Guillaume La Roque <glaroque@baylibre.com>

Re: [PATCH] arm64: dts: amlogic: meson-g12b: Fix L2 cache reference for S922X CPUs

[Neil Armstrong]

On 11/23/25 18:14, Guillaume La Roque wrote:
> The original addition of cache information for the Amlogic S922X SoC
> used the wrong next-level cache node for CPU cores 100 and 101,
> incorrectly referencing `l2_cache_l`. These cores actually belong to
> the big cluster and should reference `l2_cache_b`. Update the device
> tree accordingly.
> 
> Fixes: e7f85e6c155a ("arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC")
> Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
> ---
>   arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
> index f04efa828256..23358d94844c 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
> @@ -87,7 +87,7 @@ cpu100: cpu@100 {
>   			i-cache-line-size = <32>;
>   			i-cache-size = <0x8000>;
>   			i-cache-sets = <32>;
> -			next-level-cache = <&l2_cache_l>;
> +			next-level-cache = <&l2_cache_b>;
>   			#cooling-cells = <2>;
>   		};
>   
> @@ -103,7 +103,7 @@ cpu101: cpu@101 {
>   			i-cache-line-size = <32>;
>   			i-cache-size = <0x8000>;
>   			i-cache-sets = <32>;
> -			next-level-cache = <&l2_cache_l>;
> +			next-level-cache = <&l2_cache_b>;
>   			#cooling-cells = <2>;
>   		};
>   
> 
> ---
> base-commit: 6a23ae0a96a600d1d12557add110e0bb6e32730c
> change-id: 20251123-fixkhadas-c84da7d7c47c
> 
> Best regards,

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

Re: [PATCH] arm64: dts: amlogic: meson-g12b: Fix L2 cache reference for S922X CPUs

[Neil Armstrong]

Hi,

On Sun, 23 Nov 2025 18:14:10 +0100, Guillaume La Roque wrote:
> The original addition of cache information for the Amlogic S922X SoC
> used the wrong next-level cache node for CPU cores 100 and 101,
> incorrectly referencing `l2_cache_l`. These cores actually belong to
> the big cluster and should reference `l2_cache_b`. Update the device
> tree accordingly.
> 
> 
> [...]

Thanks, Applied to https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git (v6.19/arm64-dt)

[1/1] arm64: dts: amlogic: meson-g12b: Fix L2 cache reference for S922X CPUs
      https://git.kernel.org/amlogic/c/79482f3791c4760b9b0d8d9bfde9f1053ea3dd5e

These changes has been applied on the intermediate git tree [1].

The v6.19/arm64-dt branch will then be sent via a formal Pull Request to the Linux SoC maintainers
for inclusion in their intermediate git branches in order to be sent to Linus during
the next merge window, or sooner if it's a set of fixes.

In the cases of fixes, those will be merged in the current release candidate
kernel and as soon they appear on the Linux master branch they will be
backported to the previous Stable and Long-Stable kernels [2].

The intermediate git branches are merged daily in the linux-next tree [3],
people are encouraged testing these pre-release kernels and report issues on the
relevant mailing-lists.

If problems are discovered on those changes, please submit a signed-off-by revert
patch followed by a corrective changeset.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git
[2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
[3] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git

-- 
Neil

Re: [PATCH] arm64: dts: amlogic: meson-g12b: Fix L2 cache reference for S922X CPUs

[Anand Moon]

Hi Guillaume,

On Sun, 23 Nov 2025 at 22:44, Guillaume La Roque <glaroque@baylibre.com> wrote:
>
> The original addition of cache information for the Amlogic S922X SoC
> used the wrong next-level cache node for CPU cores 100 and 101,
> incorrectly referencing `l2_cache_l`. These cores actually belong to
> the big cluster and should reference `l2_cache_b`. Update the device
> tree accordingly.
>
> Fixes: e7f85e6c155a ("arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC")
> Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>

Reviewed-by: Anand Moon <linux.amoon@gmail.com>

Thanks
-Anand
> ---
>  arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
> index f04efa828256..23358d94844c 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
> @@ -87,7 +87,7 @@ cpu100: cpu@100 {
>                         i-cache-line-size = <32>;
>                         i-cache-size = <0x8000>;
>                         i-cache-sets = <32>;
> -                       next-level-cache = <&l2_cache_l>;
> +                       next-level-cache = <&l2_cache_b>;
>                         #cooling-cells = <2>;
>                 };
>
> @@ -103,7 +103,7 @@ cpu101: cpu@101 {
>                         i-cache-line-size = <32>;
>                         i-cache-size = <0x8000>;
>                         i-cache-sets = <32>;
> -                       next-level-cache = <&l2_cache_l>;
> +                       next-level-cache = <&l2_cache_b>;
>                         #cooling-cells = <2>;
>                 };
>
>
> ---
> base-commit: 6a23ae0a96a600d1d12557add110e0bb6e32730c
> change-id: 20251123-fixkhadas-c84da7d7c47c
>
> Best regards,
> --
> Guillaume La Roque <glaroque@baylibre.com>
>