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From: Ruidong Tian <tianruidong@linux.alibaba.com>
To: catalin.marinas@arm.com, will@kernel.org, lpieralisi@kernel.org,
	guohanjun@huawei.com, sudeep.holla@arm.com,
	xueshuai@linux.alibaba.com, linux-kernel@vger.kernel.org,
	linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	rafael@kernel.org, lenb@kernel.org, tony.luck@intel.com,
	bp@alien8.de, yazen.ghannam@amd.com, misono.tomohiro@fujitsu.com
Cc: tianruidong@linux.alibaba.com
Subject: [PATCH v4 05/17] ras: AEST: Probe RAS system architecture version
Date: Mon, 22 Dec 2025 17:43:38 +0800	[thread overview]
Message-ID: <20251222094351.38792-6-tianruidong@linux.alibaba.com> (raw)
In-Reply-To: <20251222094351.38792-1-tianruidong@linux.alibaba.com>

The RAS version of a component can be probed via its ERRDEVARCH register.

In cases where a component (e.g., SMMU) does not implement an ERRDEVARCH
register, the driver falls back to using the RAS version of the Processing
Element (PE).

Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com>
---
 arch/arm64/include/asm/ras.h |  3 +++
 drivers/ras/aest/aest-core.c | 22 ++++++++++++++++++++++
 drivers/ras/aest/aest.h      |  3 +++
 3 files changed, 28 insertions(+)

diff --git a/arch/arm64/include/asm/ras.h b/arch/arm64/include/asm/ras.h
index b6640b9972bf..da7c441252fe 100644
--- a/arch/arm64/include/asm/ras.h
+++ b/arch/arm64/include/asm/ras.h
@@ -4,6 +4,9 @@
 
 #include <linux/types.h>
 
+/* ERRDEVARCH */
+#define ERRDEVARCH_REV GENMASK(19, 16)
+
 struct ras_ext_regs {
 	u64 err_fr;
 	u64 err_ctlr;
diff --git a/drivers/ras/aest/aest-core.c b/drivers/ras/aest/aest-core.c
index f4a5119dc513..84b2fb8127ff 100644
--- a/drivers/ras/aest/aest-core.c
+++ b/drivers/ras/aest/aest-core.c
@@ -16,6 +16,27 @@ DEFINE_PER_CPU(struct aest_device, percpu_adev);
 #undef pr_fmt
 #define pr_fmt(fmt) "AEST: " fmt
 
+static int get_aest_node_ver(struct aest_node *node)
+{
+	u64 reg;
+	void *devarch_base;
+
+	if (node->type == ACPI_AEST_GIC_ERROR_NODE) {
+		devarch_base = ioremap(node->info->interface_hdr->address +
+					       GIC_ERRDEVARCH,
+				       PAGE_SIZE);
+		if (!devarch_base)
+			return 0;
+
+		reg = readl_relaxed(devarch_base);
+		iounmap(devarch_base);
+
+		return FIELD_GET(ERRDEVARCH_REV, reg);
+	}
+
+	return FIELD_GET(ID_AA64PFR0_EL1_RAS_MASK, read_cpuid(ID_AA64PFR0_EL1));
+}
+
 static int aest_init_record(struct aest_record *record, int i,
 			    struct aest_node *node)
 {
@@ -108,6 +129,7 @@ static int aest_init_node(struct aest_device *adev, struct aest_node *node,
 	node->adev = adev;
 	node->info = anode;
 	node->type = anode->type;
+	node->version = get_aest_node_ver(node);
 	node->name = alloc_aest_node_name(node);
 	if (!node->name)
 		return -ENOMEM;
diff --git a/drivers/ras/aest/aest.h b/drivers/ras/aest/aest.h
index 31131cce9928..bf0b9a49fdaa 100644
--- a/drivers/ras/aest/aest.h
+++ b/drivers/ras/aest/aest.h
@@ -61,6 +61,8 @@
 #define ERXMISC2 0x30
 #define ERXMISC3 0x38
 
+#define GIC_ERRDEVARCH 0xFFBC
+
 struct aest_access {
 	u64 (*read)(void *base, u32 offset);
 	void (*write)(void *base, u32 offset, u64 val);
@@ -141,6 +143,7 @@ struct aest_node {
 	 *              error events.
 	 */
 	unsigned long *status_reporting;
+	int version;
 
 	const struct aest_group *group;
 	struct aest_device *adev;
-- 
2.51.2.612.gdc70283dfc


  parent reply	other threads:[~2025-12-22  9:44 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-12-22  9:43 [PATCH v4 00/17] ARM Error Source Table V2 Support Ruidong Tian
2025-12-22  9:43 ` [PATCH v4 01/17] ACPI/AEST: Parse the AEST table Ruidong Tian
2025-12-22  9:43 ` [PATCH v4 02/17] ras: AEST: Add probe/remove for AEST driver Ruidong Tian
2025-12-22  9:43 ` [PATCH v4 03/17] ras: AEST: support different group format Ruidong Tian
2025-12-22  9:43 ` [PATCH v4 04/17] ras: AEST: Unify the read/write interface for system and MMIO register Ruidong Tian
2025-12-22  9:43 ` Ruidong Tian [this message]
2025-12-22  9:43 ` [PATCH v4 06/17] ras: AEST: Support RAS Common Fault Injection Model Extension Ruidong Tian
2025-12-22  9:43 ` [PATCH v4 07/17] ras: AEST: Support CE threshold of error record Ruidong Tian
2025-12-22  9:43 ` [PATCH v4 08/17] ras: AEST: Enable and register IRQs Ruidong Tian
2025-12-22  9:43 ` [PATCH v4 09/17] ras: AEST: Add cpuhp callback Ruidong Tian
2025-12-22  9:43 ` [PATCH v4 10/17] ras: AEST: Introduce AEST driver sysfs interface Ruidong Tian
2025-12-23  0:57   ` kernel test robot
2025-12-22  9:43 ` [PATCH v4 11/17] ras: AEST: Add error count tracking and debugfs interface Ruidong Tian
2025-12-22  9:43 ` [PATCH v4 12/17] ras: AEST: Allow configuring CE threshold via debugfs Ruidong Tian
2025-12-22  9:43 ` [PATCH v4 13/17] ras: AEST: Introduce AEST inject interface to test AEST driver Ruidong Tian
2025-12-22  9:43 ` [PATCH v4 14/17] ras: ATL: Unified ATL interface for ARM64 and AMD Ruidong Tian
2025-12-22  9:43 ` [PATCH v4 14/17] ras: ATL: Unify " Ruidong Tian
2025-12-22 23:34   ` kernel test robot
2025-12-25  6:58   ` kernel test robot
2025-12-22  9:43 ` [PATCH v4 15/17] ras: AEST: Add framework to process AEST vendor node Ruidong Tian
2025-12-22  9:43 ` [PATCH v4 16/17] ras: AEST: support vendor node CMN700 Ruidong Tian
2025-12-22  9:43 ` [PATCH v4 17/17] trace, ras: add ARM RAS extension trace event Ruidong Tian

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