From: Laveesh Bansal <laveeshb@laveeshbansal.com>
To: Guenter Roeck <linux@roeck-us.net>
Cc: Jonathan Corbet <corbet@lwn.net>,
linux-hwmon@vger.kernel.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org,
Laveesh Bansal <laveeshb@laveeshbansal.com>
Subject: [PATCH 2/2] hwmon: (coretemp) Add TjMax for Silvermont through Tremont Atoms
Date: Tue, 6 Jan 2026 15:54:26 +0000 [thread overview]
Message-ID: <20260106155426.547872-3-laveeshb@laveeshbansal.com> (raw)
In-Reply-To: <20260106155426.547872-1-laveeshb@laveeshbansal.com>
Add fallback TjMax values for Intel Atom processors based on Silvermont,
Airmont, Goldmont, and Tremont microarchitectures. These processors
support MSR_IA32_TEMPERATURE_TARGET for reading TjMax directly, so these
table entries serve as fallback values only when the MSR read fails
(e.g., in some virtualization scenarios).
Added processors and TjMax values:
- INTEL_ATOM_SILVERMONT (0x37, Bay Trail):
- Stepping 9 (E38xx embedded): 110C
- Other steppings (Z37xx tablet): 90C
Stepping identified from Intel E3800 Specification Update.
- INTEL_ATOM_SILVERMONT_MID (0x4a, Merrifield): 90C
- INTEL_ATOM_SILVERMONT_MID2 (0x5a, Moorefield): 90C
- INTEL_ATOM_AIRMONT (0x4c, Cherry Trail): 90C
- INTEL_ATOM_GOLDMONT (0x5c, Apollo Lake): 105C
- INTEL_ATOM_GOLDMONT_PLUS (0x7a, Gemini Lake): 105C
- INTEL_ATOM_TREMONT (0x96, Elkhart Lake): 105C
- INTEL_ATOM_TREMONT_L (0x9c, Jasper Lake): 105C
Not included (MSR reads work reliably, server/specialized chips):
- INTEL_ATOM_SILVERMONT_D (Avoton): Server, Tcase 97C
- INTEL_ATOM_GOLDMONT_D (Denverton): Server, Tcase 82C
- INTEL_ATOM_AIRMONT_NP (Lightning Mountain): Network processor
- INTEL_ATOM_TREMONT_D (Jacobsville): Server
- INTEL_ATOM_GRACEMONT (Alder Lake-N): Very new, MSR works
Reference: Intel datasheets and ARK processor specifications
- Z3600/Z3700 datasheet: https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-z36xxx-z37xxx-datasheet-vol-1.pdf
- E3845 ARK: https://www.intel.com/content/www/us/en/products/sku/78475/intel-atom-processor-e3845-2m-cache-1-91-ghz/specifications.html
- E3800 Spec Update: https://community.intel.com/cipcp26785/attachments/cipcp26785/embedded-atom-processors/4708/1/600834-329901-intel-atom-processor-e3800-product-family-su-rev015.pdf
Signed-off-by: Laveesh Bansal <laveeshb@laveeshbansal.com>
---
drivers/hwmon/coretemp.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
index ad79db5a183e..d2dfa4e30407 100644
--- a/drivers/hwmon/coretemp.c
+++ b/drivers/hwmon/coretemp.c
@@ -145,6 +145,15 @@ static const struct tjmax_model tjmax_model_table[] = {
* Also matches S12x0 (stepping 9), covered by
* PCI table
*/
+ { INTEL_ATOM_SILVERMONT, 9, 110000 }, /* Atom Bay Trail E38xx (embedded) */
+ { INTEL_ATOM_SILVERMONT, ANY, 90000 }, /* Atom Bay Trail Z37xx (tablet) */
+ { INTEL_ATOM_SILVERMONT_MID, ANY, 90000 }, /* Atom Merrifield (Z34xx) */
+ { INTEL_ATOM_SILVERMONT_MID2, ANY, 90000 }, /* Atom Moorefield (Z35xx) */
+ { INTEL_ATOM_AIRMONT, ANY, 90000 }, /* Atom Cherry Trail (Z8xxx) */
+ { INTEL_ATOM_GOLDMONT, ANY, 105000 }, /* Atom Apollo Lake (J3xxx, N3xxx, E39xx) */
+ { INTEL_ATOM_GOLDMONT_PLUS, ANY, 105000 }, /* Atom Gemini Lake (J4xxx, N4xxx, N5xxx) */
+ { INTEL_ATOM_TREMONT, ANY, 105000 }, /* Atom Elkhart Lake */
+ { INTEL_ATOM_TREMONT_L, ANY, 105000 }, /* Atom Jasper Lake */
};
static bool is_pkg_temp_data(struct temp_data *tdata)
--
2.43.0
next prev parent reply other threads:[~2026-01-06 15:55 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-06 15:54 [PATCH 0/2] hwmon: (coretemp) Documentation and TjMax table updates Laveesh Bansal
2026-01-06 15:54 ` [PATCH 1/2] Documentation: hwmon: coretemp: Update supported CPUs and TjMax values Laveesh Bansal
2026-01-13 0:01 ` Guenter Roeck
2026-01-06 15:54 ` Laveesh Bansal [this message]
2026-01-13 0:02 ` [PATCH 2/2] hwmon: (coretemp) Add TjMax for Silvermont through Tremont Atoms Guenter Roeck
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