From: Xiang-Bin Shi <eric91102091@gmail.com>
To: Borislav Petkov <bp@alien8.de>, Thomas Gleixner <tglx@kernel.org>
Cc: x86@kernel.org, linux-kernel@vger.kernel.org,
Xiang-Bin Shi <eric91102091@gmail.com>
Subject: [PATCH] x86/ibs: Fix typo in dc_l2tlb_miss comment
Date: Fri, 23 Jan 2026 15:57:19 +0800 [thread overview]
Message-ID: <20260123075719.160734-1-eric91102091@gmail.com> (raw)
The comment for dc_l2tlb_miss incorrectly describes it as a "hit".
This contradicts the field name and the actual bit definition.
Fix the comment to correctly describe it as a "miss".
Signed-off-by: Xiang-Bin Shi <eric91102091@gmail.com>
---
arch/x86/include/asm/amd/ibs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/amd/ibs.h b/arch/x86/include/asm/amd/ibs.h
index 3ee5903982c2..fcc8a5abe54e 100644
--- a/arch/x86/include/asm/amd/ibs.h
+++ b/arch/x86/include/asm/amd/ibs.h
@@ -110,7 +110,7 @@ union ibs_op_data3 {
__u64 ld_op:1, /* 0: load op */
st_op:1, /* 1: store op */
dc_l1tlb_miss:1, /* 2: data cache L1TLB miss */
- dc_l2tlb_miss:1, /* 3: data cache L2TLB hit in 2M page */
+ dc_l2tlb_miss:1, /* 3: data cache L2TLB miss in 2M page */
dc_l1tlb_hit_2m:1, /* 4: data cache L1TLB hit in 2M page */
dc_l1tlb_hit_1g:1, /* 5: data cache L1TLB hit in 1G page */
dc_l2tlb_hit_2m:1, /* 6: data cache L2TLB hit in 2M page */
--
2.34.1
next reply other threads:[~2026-01-23 7:59 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-23 7:57 Xiang-Bin Shi [this message]
2026-02-02 21:04 ` [tip: perf/core] " tip-bot2 for Xiang-Bin Shi
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