* [PATCH] x86/ibs: Fix typo in dc_l2tlb_miss comment
@ 2026-01-23 7:57 Xiang-Bin Shi
2026-02-02 21:04 ` [tip: perf/core] " tip-bot2 for Xiang-Bin Shi
0 siblings, 1 reply; 2+ messages in thread
From: Xiang-Bin Shi @ 2026-01-23 7:57 UTC (permalink / raw)
To: Borislav Petkov, Thomas Gleixner; +Cc: x86, linux-kernel, Xiang-Bin Shi
The comment for dc_l2tlb_miss incorrectly describes it as a "hit".
This contradicts the field name and the actual bit definition.
Fix the comment to correctly describe it as a "miss".
Signed-off-by: Xiang-Bin Shi <eric91102091@gmail.com>
---
arch/x86/include/asm/amd/ibs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/amd/ibs.h b/arch/x86/include/asm/amd/ibs.h
index 3ee5903982c2..fcc8a5abe54e 100644
--- a/arch/x86/include/asm/amd/ibs.h
+++ b/arch/x86/include/asm/amd/ibs.h
@@ -110,7 +110,7 @@ union ibs_op_data3 {
__u64 ld_op:1, /* 0: load op */
st_op:1, /* 1: store op */
dc_l1tlb_miss:1, /* 2: data cache L1TLB miss */
- dc_l2tlb_miss:1, /* 3: data cache L2TLB hit in 2M page */
+ dc_l2tlb_miss:1, /* 3: data cache L2TLB miss in 2M page */
dc_l1tlb_hit_2m:1, /* 4: data cache L1TLB hit in 2M page */
dc_l1tlb_hit_1g:1, /* 5: data cache L1TLB hit in 1G page */
dc_l2tlb_hit_2m:1, /* 6: data cache L2TLB hit in 2M page */
--
2.34.1
^ permalink raw reply [flat|nested] 2+ messages in thread* [tip: perf/core] x86/ibs: Fix typo in dc_l2tlb_miss comment
2026-01-23 7:57 [PATCH] x86/ibs: Fix typo in dc_l2tlb_miss comment Xiang-Bin Shi
@ 2026-02-02 21:04 ` tip-bot2 for Xiang-Bin Shi
0 siblings, 0 replies; 2+ messages in thread
From: tip-bot2 for Xiang-Bin Shi @ 2026-02-02 21:04 UTC (permalink / raw)
To: linux-tip-commits
Cc: Xiang-Bin Shi, Peter Zijlstra (Intel), x86, linux-kernel
The following commit has been merged into the perf/core branch of tip:
Commit-ID: 171efc70097a9f5f207461bed03478a1b0a3dfa6
Gitweb: https://git.kernel.org/tip/171efc70097a9f5f207461bed03478a1b0a3dfa6
Author: Xiang-Bin Shi <eric91102091@gmail.com>
AuthorDate: Fri, 23 Jan 2026 15:57:19 +08:00
Committer: Peter Zijlstra <peterz@infradead.org>
CommitterDate: Mon, 02 Feb 2026 22:01:07 +01:00
x86/ibs: Fix typo in dc_l2tlb_miss comment
The comment for dc_l2tlb_miss incorrectly describes it as a "hit".
This contradicts the field name and the actual bit definition.
Fix the comment to correctly describe it as a "miss".
Signed-off-by: Xiang-Bin Shi <eric91102091@gmail.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260123075719.160734-1-eric91102091@gmail.com
---
arch/x86/include/asm/amd/ibs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/amd/ibs.h b/arch/x86/include/asm/amd/ibs.h
index 3ee5903..fcc8a5a 100644
--- a/arch/x86/include/asm/amd/ibs.h
+++ b/arch/x86/include/asm/amd/ibs.h
@@ -110,7 +110,7 @@ union ibs_op_data3 {
__u64 ld_op:1, /* 0: load op */
st_op:1, /* 1: store op */
dc_l1tlb_miss:1, /* 2: data cache L1TLB miss */
- dc_l2tlb_miss:1, /* 3: data cache L2TLB hit in 2M page */
+ dc_l2tlb_miss:1, /* 3: data cache L2TLB miss in 2M page */
dc_l1tlb_hit_2m:1, /* 4: data cache L1TLB hit in 2M page */
dc_l1tlb_hit_1g:1, /* 5: data cache L1TLB hit in 1G page */
dc_l2tlb_hit_2m:1, /* 6: data cache L2TLB hit in 2M page */
^ permalink raw reply [flat|nested] 2+ messages in thread
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